Cache Coherency Mechanisms in RISC-V Multicore Architectures (eBook)

Wei Kun Tan, Kim Ho Yeap (Autoren)

eBook Download: PDF

2025
155 Seiten
Cambridge Scholars Publishing (Verlag)
978-1-0364-4481-5 (ISBN)

Infos

In the rapidly evolving world of multicore systems, ensuring cache coherency is crucial for maintaining data consistency and system performance. This book delves deep into the complexities of cache coherency in parallel computing environments, offering a comprehensive exploration of both snoop-based and directory-based protocols. Detailed insights are provided into various protocols, including MSI, MESI, MOSI, MOESI, and Write-Once, analysing their unique advantages and trade-offs. Leveraging the open-source RISC-V architecture, known for its scalability and modularity, the book presents the design and development of a scalable cache coherency fabric tailored for RISC-V multicore systems. Through detailed simulations using SystemVerilog and ModelSim, the book rigorously examines the fabric's ability to maintain memory consistency across multiple cores, providing valuable findings that contribute to the advancement of multicore processor design. Whether you are a researcher, engineer, or student, this book offers an essential guide to understanding and optimizing cache coherency in multicore systems.

Produkt-Details

• Erscheint lt. Verlag: 7.3.2025
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• ISBN-10: 1-0364-4481-3 / 1036444813
• ISBN-13: 978-1-0364-4481-5 / 9781036444815