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Cache Coherency Mechanisms in RISC-V Multicore Architectures - Kim Ho Yeap, Wei Kun Tan

Cache Coherency Mechanisms in RISC-V Multicore Architectures

Buch | Hardcover
155 Seiten
2025 | Unabridged edition
Cambridge Scholars Publishing (Verlag)
978-1-0364-4480-8 (ISBN)
CHF 113,45 inkl. MwSt
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In the rapidly evolving world of multicore systems, ensuring cache coherency is crucial for maintaining data consistency and system performance. This book delves deep into the complexities of cache coherency in parallel computing environments, offering a comprehensive exploration of both snoop-based and directory-based protocols. Detailed insights are provided into various protocols, including MSI, MESI, MOSI, MOESI, and Write-Once, analysing their unique advantages and trade-offs. Leveraging the open-source RISC-V architecture, known for its scalability and modularity, the book presents the design and development of a scalable cache coherency fabric tailored for RISC-V multicore systems. Through detailed simulations using SystemVerilog and ModelSim, the book rigorously examines the fabric's ability to maintain memory consistency across multiple cores, providing valuable findings that contribute to the advancement of multicore processor design. Whether you are a researcher, engineer, or student, this book offers an essential guide to understanding and optimizing cache coherency in multicore systems.

Kim Ho Yeap, an associate professor at Universiti Tunku Abdul Rahman, Malaysia, and a senior member of IEEE, has published more than 180 peer-reviewed articles and 3 patents. Two of his published works impacted the design of the ALMA radio telescope's receiver optics. Yeap holds Chartered Engineer, Professional Engineer, and ASEAN Chartered Professional Engineer statuses, received teaching excellence and Intel Kudos awards, and secured close to 30 research grants.Wei Kun Tan holds a bachelor's degree with Honours in Electronic and Communications Engineering and a master's in Engineering Electronic Systems from Universiti Tunku Abdul Rahman. Presently, he serves as a design verification engineer at Intel Altera.

Erscheinungsdatum
Verlagsort Newcastle upon Tyne
Sprache englisch
Maße 148 x 212 mm
Themenwelt Mathematik / Informatik Informatik Theorie / Studium
Technik Elektrotechnik / Energietechnik
ISBN-10 1-0364-4480-5 / 1036444805
ISBN-13 978-1-0364-4480-8 / 9781036444808
Zustand Neuware
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