System Level ESD Co-Design (eBook)

Charvaka Duvvury, Harald Gossner (Herausgeber)

eBook Download: PDF

2017
John Wiley & Sons (Verlag)
978-1-118-86188-2 (ISBN)

Infos

An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. This pioneering book presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from 'hard' to 'soft' types are considered to review simulation and tool applications that can be used.

The principal focus of System Level ESD Co-Design is defining and establishing the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers' system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance.

With contributions from Robert Ashton, Jeffrey Dunnihoo, Micheal Hopkins, Pratik Maheshwari, David Pomerenke, Wolfgang Reinprecht, and Matti Usumaki, readers benefit from hands-on experience and in-depth knowledge in topics ranging from ESD design and the physics of system ESD phenomena to tools and techniques to address soft failures and strategies to design ESD-robust systems that include mobile and automotive applications.

The first dedicated resource to system-level ESD co-design, this is an essential reference for industry ESD designers, system builders, IC suppliers and customers and also Original Equipment Manufacturers (OEMs).

Key features:

• Clarifies the concept of system level ESD protection.
• Introduces a co-design approach for ESD robust systems.
• Details soft and hard ESD fail mechanisms.
• Detailed protection strategies for both mobile and automotive applications.
• Explains simulation tools and methodology for system level ESD co-design and overviews available test methods and standards.
• Highlights economic benefits of system ESD co-design.

Charvaka Duvvury, formerly Texas Instruments, USA
Charvaka Duvvury, formerly of Texas Instruments, is currently working as a technical consultant on ESD design methods and ESD qualification support. He has published over 150 technical papers and holds more than 70 patents. He is a co-founder and co-chair of the Industry Council on ESD Target Levels and has been serving as Board of Director of the ESDA since 1997 promoting university education and research in ESD technology.
Harald Gossner, Intel, Germany
Harald Gossner is Senior Principal Engineer at Intel where for 15 years he has worked on the development of ESD protection concepts with Siemens and Infineon Technologies. In 2010 he has joined Intel Mobile Communications overseeing the development of robust mobile systems. Harald has authored and co-authored more than 100 technical papers and one book in the field of ESD and device physics. He holds more than 60 patents on the same topic. In 2006 he became cofounder and co-chair of the Industry Council on ESD Target Levels.

Inhalt

Cover 1
Title Page 5
Copyright 6
Contents 7
List of Contributors 15
Preface 17
Acronyms 19
About the Book 23
Chapter 1 Introduction 25
1.1 Definition of Co-Design 25
1.2 Overview of the Book 26
1.3 Challenges of System Level ESD Protection 26
1.4 Importance of System Level Protection 26
1.5 Industry-Wide Perception 29
1.6 Purpose and Motivation 32
1.7 Organization and Approach 32
1.8 Outcome for the Reader 36
Acknowledgments 36
References 36
Chapter 2 Component versus System Level ESD 38
2.1 ESD Threat in the Real World 38
2.1.1 ESD Control 38
2.1.2 ESD Failure Types 39
2.1.3 ESD Protection Areas 40
2.1.4 ESD Stress Models 41
2.2 Component ESD Qualification 41
2.2.1 Component ESD Tests 41
2.2.2 ESD Levels for IC Production 42
2.2.3 Implications for System Level ESD 44
2.2.4 ESD Technology Roadmap 44
2.3 System Level ESD Tests 45
2.3.1 IEC 61000-4-2 46
2.4 ISO 10605 53
2.5 IEC 61000-4-5 55
2.5.1 System Applications 56
2.5.2 Misconceptions and Miscorrelation of Component and System Level Tests 59
2.5.3 Hard Failures Due to IEC Testing 66
2.6 Soft Failures Due to IEC Testing 66
Acknowledgments 67
References 67
Chapter 3 System Level Testing for ESD Susceptibility 70
3.1 Introduction 70
3.2 Objectives of System Level Testing 71
3.3 Compliance to ESD Standards 71
3.3.1 Legal Compliance Requirements 71
3.3.2 Compliance to Industry Requirements 72
3.4 Testing for Product Reliability 72
3.5 Standards Requirements for System Level Testing 73
3.5.1 IEC 61000-4-2 73
3.5.2 Automotive Standards for ESD 82
3.5.3 Medical Standards for ESD 84
3.5.4 Avionics Standards for ESD 85
3.5.5 Military ESD Standards 85
3.6 Using the IEC Simulator for Device Testing 86
3.7 Cable Discharge (CDE) Testing 87
3.7.1 Shielded Cables 89
3.7.2 Unshielded Cables 89
3.7.3 Modified Transmission Line Pulsers (TLP) for CDE Testing 90
3.8 Evaluation of Test Results 91
3.8.1 Hard Failure Evaluation 91
3.8.2 Soft Failure Evaluation 91
3.9 The Quick Fix vs Root Cause Determination 91
3.10 Determining Root Cause of System Level ESD 92
3.11 Reproducibility of System Level ESD Tests 94
Acknowledgments 96
References 96
Chapter 4 PCB/IC Co-Design Concepts for SEED 98
4.1 On-Chip System ESD Protection 98
4.1.1 HBM and CDM vs IEC 98
4.1.2 TLP Characterization 100
4.1.3 TLP Correlation Issues 102
4.2 Off-Chip ESD Protection 103
4.3 Concept of PCB/IC Co-Design 106
4.3.1 On-Chip IEC Protection Solutions 108
4.4 Introduction to System Efficient ESD Design 108
4.4.1 Design Methods for SEED 114
4.4.2 Basic Simulations using SEED 115
4.4.3 USB Design using SEED 118
4.5 Characterization for Hard Failures 121
4.6 Simulation of System Level ESD Discharge Paths 122
4.6.1 Simulation Approach 122
4.6.2 Tools 125
4.6.3 ESD Model Types 127
4.6.4 Extraction of PCB Paths 128
4.6.5 Models of PCB Devices 128
4.6.6 Characterization of IO Cells 130
4.6.7 Power Clamp Models 136
4.6.8 Model for Stress Waveform 138
4.7 Characterization of Soft Failures 140
4.7.1 Purpose and Basic Concept 140
4.7.2 Pin Specific Soft Failure Characterization 144
4.7.3 Soft Failures Related to Signal Integrity Problems 147
4.8 Summary of SEED Characterization 149
Acknowledgments 150
References 151
Chapter 5 Hard Failures and PCB Protection Devices 153
5.1 Introduction 153
5.2 ESD Damage to ICs 153
5.3 Protection Methods 154
5.3.1 Classification of TVS Devices 157
5.4 Characteristics of Protection Devices 158
5.4.1 Current Limiting Devices 158
5.4.2 TVS Properties in Their Off-State 159
5.4.3 Protection Properties of TVS Devices 161
5.5 Types of Protection Devices for ESD 166
5.5.1 Silicon Based TVS Devices 167
5.5.2 Metal Oxide Varistors 178
5.5.3 Polymer Voltage Suppressors 179
5.5.4 Gas Discharge Tubes 180
5.5.5 Spark Gaps on PCBs 182
5.5.6 Thyristor Surge Protection Devices 183
5.5.7 Ferrite Beads 183
5.5.8 Passive Components 185
5.5.9 Common Mode Filters 186
5.6 Primary and Secondary Protection 187
5.7 Evaluating IC Pins 188
5.8 Choosing ESD Protection Devices 188
5.8.1 Coordination between TVS Device and Sensitive Nodes 189
5.9 Summary 191
References 191
Chapter 6 Soft Failure Mechanisms and PCB Design Measures 193
6.1 Introduction 193
6.2 Are HBM, CDM, MM, and Latch-Up Results Meaningful Soft Failures? 195
6.3 Classification of Soft Failure Modes 197
6.3.1 In-Band/Out-of-Band with Respect to Voltage 198
6.3.2 In-Band/Out-of-Band with Respect to Pulse Width 199
6.3.3 Local vs Distant Errors 200
6.3.4 Amplified/Non-amplified Soft Failures 200
6.4 Optimized System Level Testing 202
6.5 Soft Failure Characterization Methods 206
6.5.1 Susceptibility Scanning 207
6.5.2 Current Spreading Reconstruction 214
6.5.3 Local Injection 215
6.5.4 Software-Based Methods for Soft Failure Analysis 225
6.6 Soft Failure Examples 229
6.6.1 Example 1: Soft Failure Caused by Field Injection on a DUT (Mini Photo Frame) 229
6.6.2 Example 2: PLL Disturbance Measurement 231
6.6.3 Example 3: Direct Field Coupling on the USB Data Bus 236
6.6.4 Example 4: Direct Injection on the MIPI Bus Interface 239
6.7 Countermeasure Examples 240
6.7.1 Divert Current 240
6.7.2 Filtering 241
6.7.3 Shielding 241
6.7.4 Secondary ESD Avoidance 242
6.7.5 Improved Connector-Cable Shield Connection 242
6.7.6 Enclosure to Connector Shield Junction 242
6.7.7 Firmware 242
6.7.8 Reducing Crosstalk 243
6.7.9 Reduce ESD Current by Resistance 244
6.7.10 Avoid ESD 246
6.8 The Way Forward 247
Acknowledgment 254
References 255
Chapter 7 ESD in Mobile Devices 258
7.1 Introduction 258
7.2 ESD Energy Path in Mobile Device 258
7.3 ESD Generation Examples on a Large Scale 263
7.3.1 Large Machines Generating Charges to Their Isolated Bodies 263
7.3.2 Tribo-Electric Series 264
7.3.3 Charge Generated by a Person Inside a Car 264
7.3.4 The Charge Generated to Mobile Device by Accident in Grounded System 265
7.3.5 Alternative Discharging Paths at Connection Moment 268
7.3.6 Charge Behavior at Insulator Surface 268
7.3.7 Example of Consumer Level Charge Generation with Simple Device 270
7.4 Relation between Electrostatic Discharge Immunity Test and Real-World Discharge Waveforms 272
7.5 Laboratory Test Methods 272
7.6 Fast ESD and Slow ESD Concepts 273
7.7 Fast-ESD and Slow-ESD in a Mobile Device 274
7.7.1 Example of Ground Level Bounce Relative to an External Module 275
7.8 Isolating a Mobile Device 276
7.8.1 Example 1: Material Thickness 276
7.8.2 Example 2: Solid Glue 277
7.8.3 Example 3: Positioning Holes in a Rubberized Key Mat 279
7.8.4 Example 4: Induced Electric Field 279
7.9 Shielding a Mobile Device 281
7.10 Orientation Effects on ESD Path 283
7.10.1 ESD Path Example: Phone Face Up on Table 283
7.10.2 ESD Path Example: Phone Face Down on the Table 287
7.11 ESD Design in Practice 288
7.11.1 Grounding Challenges in Practice 288
7.12 PCB Layout Considerations of Metal Shielding "Cans" 291
7.12.1 Components Near the Edge of the Shield 292
7.13 ESD Protection for Cable Interfaces 293
7.13.1 Cable Placement and Common Mode Current in a Mobile Device 294
7.13.2 Localizing Noise Current with Alternate Cabling Placement 298
7.13.3 Cable Interface Protection Components 299
7.14 Common Mode Impedance Concerns for Layout 304
7.14.1 Common Mode Impedance Challenges in the Grounding Paths 304
7.14.2 Signals with Shared Common Mode Impedance 304
7.14.3 Isolating Signals with Shield Grounded to Internal PCB Layers 306
7.14.4 Simulated Example of Ground Impedance Effect on ESD/EMI Filter Performance 307
7.14.5 ESD Protection on Stacked Chips 307
7.14.6 Layout Concerns around the Periphery and PCB Cutouts 309
7.15 ESD and Software Considerations in Mobile Devices 311
7.15.1 Role of Software in EMC and ESD Design 311
7.15.2 Signal Sensitivity to ESD Examples 312
7.15.3 Delayed Effects on Software from ESD Events 314
7.16 Software Versions Utilized in Early ESD Immunity Testing 315
7.17 Conclusion 316
References 316
Chapter 8 ESD for Automotive Applications 318
8.1 Introduction and Historical Aspects 318
8.1.1 Why Do Automotive Components Require High ESD Levels? 318
8.1.2 Field Return Rate of Automotive Products due to System Level ESD Events 320
8.1.3 ESD Related Field Returns Because of Incomplete Specification or Missing System Protection 321
8.2 Automotive Components 323
8.2.1 Communication Systems CAN, LIN, FlexRay 323
8.2.2 Power Supply Systems as DCDC Converter, Alternator, LDO 327
8.2.3 Sensors and Sensor Interfaces 328
8.2.4 Keyless Entry/Go with Components Exposed to Human Touching/Handling 335
8.2.5 Power Steering, Drive by Wire, Gearbox, Hybrid Systems, Recuperation 337
8.2.6 LED Lights, Entertainment, Navigation, and Audio 337
8.3 Design Constraints, Operating Voltage, and Overvoltage Tolerance 339
8.3.1 "Normal Overvoltage Range": 18 V into 5 V/3 V/1.8 V 339
8.3.2 Load Dump 339
8.3.3 Loss of Ground, Dual Polarity, and Reverse Polarity 341
8.3.4 EMC Tolerance versus ESD Robustness (Fast Transients) 343
8.3.5 Leakage Current versus ESD Robustness (Pre-Pulse Voltage) 344
8.3.6 Latch-Up-Free ESD Protection versus Snapback Devices 345
8.4 On-Board ESD Protection and Internal ESD Protection 348
8.4.1 Characterization Methods to Get Relevant Data for External ESD Devices 348
8.4.2 ESD Design Window Using External Protection Elements (TVS) 348
8.4.3 Optimizing On-Chip ESD Protections to Match Board Level Protection 348
8.4.4 On-Board Ground Shift due to System ESD Events 349
8.4.5 Secondary Effects as Transient Disturbances to "Internal" Pins (Lateral Coupling) 350
8.4.6 Pin Placement, External Passive Components, and Board Layout Constraints 352
8.5 Verification and Qualification 353
8.5.1 Safe Operating Area Check to Verify Overvoltage Tolerance 353
8.5.2 ESD Design Rule Check to Verify ESD Concept and Constraints 354
8.5.3 ESD Tests on Chip Level HBM/CDM 355
8.5.4 TLP Characterization of Product to Meet SEED 355
8.5.5 System ESD Tests on Board Level up to the Level of Failure 355
8.5.6 No-Gos in Terms of ESD Design 356
8.6 Conclusion 356
References 357
Chapter 9 Future Applications of SEED Methodology 358
9.1 Refinement of Models 358
9.2 Limitations of Simulation and Beyond 361
9.2.1 Relation of SEED to System ESD Tests 361
9.2.2 Outlook to a Comprehensive Design Verification 365
9.3 Advances toward High-Speed Systems 366
9.3.1 USB and HDMI Challenges 367
9.4 Issues and Challenges of System Protection 369
9.4.1 USB 2.0 versus USB 3.0 369
9.4.2 USB 2.0/3.0 versus HDMI 370
9.4.3 Automotive Technologies 370
9.4.4 IC Package Technologies 371
9.4.5 PCB Technologies 371
9.4.6 Optical Interfaces 372
9.4.7 Polymer Material Applications 372
9.5 Benefits for Next Generation Systems 373
9.5.1 Harmonized Approach for Component to System Protection 373
9.5.2 IEC Specification Requirements 374
9.5.3 Cost of System Protection 375
Acknowledgments 375
References 375
Chapter 10 Co-Design Trade-Offs: Balancing Robustness, Performance, and Cost 377
10.1 Co-Designing across Functional and Corporate Boundaries 377
10.1.1 Component (Factory) versus System (End User) ESD Issues 377
10.1.2 Probabilities and Uncertainties of System ESD Costs 378
10.1.3 Bounded and Cumulative ESD Failure Probability 379
10.1.4 Product and Organizational Response to ESD Failure 381
10.1.5 The Reality of the "Real Cost of ESD" 382
10.1.6 Co-Designing a Solution 382
10.2 ESD Goals and Constraints 383
10.2.1 The Co-Design Gamut 383
10.2.2 ESD Margin Requirement Based on Unknown Probabilities 384
10.2.3 Extreme and Abusive Users 385
10.2.4 Ignoring the "Long Tail" Events 387
10.2.5 Capturing Quantitative System Fault Data 388
10.2.6 ESD Sousveillance 388
10.2.7 Beyond ESD Sousveillance 389
10.2.8 Vulnerabilities in the Meantime 389
10.3 Costs of System and Component ESD Susceptibility 390
10.3.1 Poor User Experience 390
10.3.2 Quantifying User Experience 391
10.3.3 Failure Analysis and Customer Return Costs 391
10.4 Costs of Improving System and Component ESD Robustness 393
10.4.1 Component Costs 393
10.4.2 Reduced Profit Margin 394
10.4.3 Reduced Performance 394
10.4.4 Co-Design Cost Allocation Example 395
10.4.5 Alternative Cost Reductions with Performance Enhancement 396
10.4.6 Increased Time-to-Market and Negative TVS Pricing 399
10.5 Defining the Interaction and Trade-off Matrix 400
10.5.1 Performance 400
10.5.2 Price 401
10.5.3 Robustness 401
10.6 Assigning the Costs of Failure Criteria 402
10.7 System Development Triangle Co-Design Contributions 403
10.7.1 Function Vendor Partitions (CPU, ASIC, Interface Device) 404
10.8 Product Planning Guidelines 404
10.8.1 Set Realistic Robustness Goals Early 404
10.8.2 Responsibilities of the Product Design Team 405
10.8.3 Responsibilities of the Product Testing and Qualification Team 405
10.8.4 Responsibility for Line Returns from Manufacturing 405
10.8.5 Responsibility for Field Returns from the Customer 405
10.8.6 Organizational Interaction with Vendors 405
10.9 Validating Co-Design Trade-off Decisions 406
10.9.1 Historical Data Availability 406
10.9.2 Difficulties of Cost Identification and Assignment 407
10.9.3 Dangers of the "Keep Your Head Down" Mentality 408
10.9.4 Balancing Low-Level Problems with High-Profile Exposure 409
10.10 Conclusions on Co-Design Economics 411
References 411
Glossary 413
Index 415
Supplemental Images 425
EULA 435

Rezensionen

System Efficient ESD design (SEED) has been an active topic over recent years among ESD designers and the electronics industry as a whole. For this book, Charvaka Duvvury and Harald Gossner along with several contributing authors, have collected an extensive package of knowledge relating to electronic system EMC/ESD co-design. Challenges with EMC/ESD designs vary depending on the industry branch, and by having a specific expertise for EMC testing, semiconductors, automotive and mobile phones business area the book creates both a broad and in deep viewpoint of the SEED methodology. I strongly recommend this book to all electronics system designers to boost their knowledge and to arm them with the tools to predict and prevent ESD or EMC related challenges within future electronic designs.

Passi Tamminen, EMC Specialist at Microsoft, Finland

Produkt-Details

• Erscheint lt. Verlag: 5.5.2017
• Reihe/Serie: IEEE Press
• Reihe/Serie: Wiley - IEEE
• Sprache: englisch
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Circuit Theory & Design • Electrical & Electronics Engineering • Elektrotechnik u. Elektronik • ESD co-design • ESD in Automotive systems • ESD in Mobile systems • ESD soft failures • Halbleiter • IEC 61000-4-2 • Leistungselektronik • PCB protection • Power Electronics • Schaltkreise - Theorie u. Entwurf • semiconductors • System ESD simulations • system level ESD • TVS diode
• ISBN-10: 1-118-86188-4 / 1118861884
• ISBN-13: 978-1-118-86188-2 / 9781118861882