System Level ESD Co-Design (eBook)

Charvaka Duvvury, Harald Gossner (Herausgeber)

eBook Download: EPUB

2015
John Wiley & Sons (Verlag)
978-1-118-86184-4 (ISBN)

Infos

An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. This pioneering book presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from ‘hard’ to ‘soft’ types are considered to review simulation and tool applications that can be used.

The principal focus of System Level ESD Co-Design is defining and establishing the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers' system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance.

With contributions from Robert Ashton, Jeffrey Dunnihoo, Micheal Hopkins, Pratik Maheshwari, David Pomerenke, Wolfgang Reinprecht, and Matti Usumaki, readers benefit from hands-on experience and in-depth knowledge in topics ranging from ESD design and the physics of system ESD phenomena to tools and techniques to address soft failures and strategies to design ESD-robust systems that include mobile and automotive applications.

The first dedicated resource to system-level ESD co-design, this is an essential reference for industry ESD designers, system builders, IC suppliers and customers and also Original Equipment Manufacturers (OEMs).

Key features:

•          Clarifies the concept of system level ESD protection.
•          Introduces a co-design approach for ESD robust systems.
•          Details soft and hard ESD fail mechanisms.
•          Detailed protection strategies for both mobile and automotive applications.
•          Explains simulation tools and methodology for system level ESD co-design and overviews available test methods and standards.
•          Highlights economic benefits of system ESD co-design.

Autor

Charvaka Duvvury, formerly Texas Instruments, USA Charvaka Duvvury, formerly of Texas Instruments, is currently working as a technical consultant on ESD design methods and ESD qualification support. He has published over 150 technical papers and holds more than 70 patents. He is a co-founder and co-chair of the Industry Council on ESD Target Levels and has been serving as Board of Director of the ESDA since 1997 promoting university education and research in ESD technology. Harald Gossner, Intel, Germany Harald Gossner is Senior Principal Engineer at Intel where for 15 years he has worked on the development of ESD protection concepts with Siemens and Infineon Technologies. In 2010 he has joined Intel Mobile Communications overseeing the development of robust mobile systems. Harald has authored and co-authored more than 100 technical papers and one book in the field of ESD and device physics. He holds more than 60 patents on the same topic. In 2006 he became cofounder and co-chair of the Industry Council on ESD Target Levels.

Rezensionen

System Efficient ESD design (SEED) has been an active topic over recent years among ESD designers and the electronics industry as a whole. For this book, Charvaka Duvvury and Harald Gossner along with several contributing authors, have collected an extensive package of knowledge relating to electronic system EMC/ESD co-design. Challenges with EMC/ESD designs vary depending on the industry branch, and by having a specific expertise for EMC testing, semiconductors, automotive and mobile phones business area the book creates both a broad and in deep viewpoint of the SEED methodology. I strongly recommend this book to all electronics system designers to boost their knowledge and to arm them with the tools to predict and prevent ESD or EMC related challenges within future electronic designs.

Passi Tamminen, EMC Specialist at Microsoft, Finland

Textauszug

Acronyms

ADB	Android debug bridge

ADS	Advanced Design System

AEC	Automotive Electronics Council

AMR	absolute maximum rating

ANSI	American National Standards Institute

ASIC	application specific integrated circuit

ASIP™

application specific integrated passive™

ASP	average selling price

ASTM	American Society for Testing and Materials

ATE	automated test equipment

AVL	approved vendor list

BCI	bulk current injection

BER	bit error rate

BGA	ball grid array

BOM	bill of materials

BSOD	blue screen of death

CAN	controller area network

CBE	charged board event

CCE	charged cable event

CCTLP

charge coupled transmission line pulse

CDE	cable discharge event

CDF	cumulative distribution function

CDM	charged-device model

CFB	chip ferrite bead

CM	contract manufacturer

CMC	common mode choke

CMF	common mode filter

CMOS	complementary metal oxide semiconductor

CO	central office

COTS	commercial off-the-shelf

CPE	customer premises equipment

CPU	central processing unit

CRC	cyclic redundancy check

dB

decibel

dBm	decibel-milliwatt

DC	direct current

DDR	double data rate

DIP	dual inline package

DMOS	double-diffused metal oxide semiconductor

DPI	direct power injection

DSP	digital signal processing

DUT	device under test

DVI	digital visual interface

ECU	electronic control unit

EDA	electronic design automation

EFT	electrical fast transients

EM	electromagnetic

EMC	electromagnetic compatibility

EMI	electromagnetic interference

EMMI	emission microscopy

EOS	electrical overstress

EPA	ESD protected area

eSATA

external serial advanced technology attachment

ESD	electrostatic discharge

ESDA	Electrostatic Discharge Association

ESR	equivalent series resistance

EU	European Union

EUT	equipment under test

FA	failure analysis

FB	ferrite bead

FFT	fast Fourier transform

FM	frequency modulation

FTC	Federal Trade Commission

GDT	gas discharge tube

GCNMOS

gate coupled n-channel metal oxide semiconductor

GGNMOS

grounded gate n-channel metal oxide semiconductor

GND	“ground” – negative voltage supply

GPIO	general purpose IO

GPU	graphic processing unit

GRP	ground reference plane

HBM	human body model

HCP	horizontal coupling plane

HDMI	high definition multimedia interface

HMM	human metal model

HSS	(HSSL) high speed serial link

IBIS	input/output buffer info specification

IC	integrated circuit

ID	identification

IDDQ	component quiescent supply current

IEC	International Electrotechnical Commission

IMD	inter-modulation distortion

IO	input/output

IP	intellectual property

IPR	intellectual property rights

ISO	International Organization for Standardization

IT	information technology

IT2	failure current under ESD conditions

JEDEC

Joint Electronic Devices Engineering Council

JEITA

Japan Electronics and Information Technology Industries Association

LC	inductor/capacitor network

LCD	liquid crystal display

LDO	low drop out (voltage regulator)

LED	light emitting diode

LIN	local interconnect network

LU

latch-up

LVDS	low voltage differential signaling

MEMS	microelectromechanical system

MID	molded interconnect device

MIL-HDBK

Military Handbook

Mil-PRF

Military Performance Specifications

Mil-STD

Military Standard

MIPI	mobile industry processor interface

MM	machine model

MOSFET

metal oxide semiconductor field effect transistor

MOV	metal oxide varistor

NF	noise frequency

OBD	on-board diagnostics

ODM	original design manufacturer

OEM	original equipment manufacturer

OMAP	Open Media Applications Platform

OTG

on-the-go

PCB	printed circuit board

PERC	programmable electrical rule check

PHY	physical layer

PICC	proximity IC cards

PLL	phase locked loop

PN	silicon PN junction

POST	power-on self tests

PVS	polymer voltage suppressor

RC	resistor/capacitor network

RF	radio frequency

RH	relative humidity

RLC	resistor/inductor/capacitor network

RP	residual pulse

RPS	residual pulse stress

RX

receiver

SATA	serial advanced technology attachment

SAW	surface acoustic wave

SCR	silicon controlled rectifier

SD	secure digital (memory card format)

SERDES

serializer/deserializer

SIM	subscriber identity module

SiP	system-in-package

SMA	sub-miniature version A

SMD	surface mount device

SMT	surface mount technology

SOA	safe operating area

SoC	system-on-chip

SoF	start of...

Produkt-Details

• Erscheint lt. Verlag: 4.8.2015
• Reihe/Serie: IEEE Press
• Reihe/Serie: Wiley - IEEE
• Reihe/Serie: Wiley - IEEE
• Sprache: englisch
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Circuit Theory & Design • Electrical & Electronics Engineering • Elektrotechnik u. Elektronik • ESD co-design • ESD in Automotive systems • ESD in Mobile systems • ESD soft failures • Halbleiter • IEC 61000-4-2 • Leistungselektronik • PCB protection • Power Electronics • Schaltkreise - Theorie u. Entwurf • semiconductors • System ESD simulations • system level ESD • TVS diode
• ISBN-10: 1-118-86184-1 / 1118861841
• ISBN-13: 978-1-118-86184-4 / 9781118861844