ESD Testing (eBook)

From Components to Systems

Steven H. Voldman (Autor)

eBook Download: EPUB

2016
John Wiley & Sons (Verlag)
9781118707159 (ISBN)

Infos

Dr Steven H. Voldman, IEEE Fellow, Vermont, USA Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for 'Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.' Voldman was a member of the semiconductor development of IBM for 25 years as well as a consultant for TSMC, and Samsung Electronics. Dr. Voldman initiated the first transmission line pulse (TLP) standard development team, and  a participant in the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2013, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP.He initiated the 'ESD on Campus' program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40  universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China.  Dr. Voldman teaches short courses and tutorials on ESD, latchup, patenting, and invention.

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With the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance. ESD Testing: From Components to Systems updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup. Key features: Provides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5. Discusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP). Describes both conventional testing and new testing techniques for both chip and system level evaluation. Addresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods. Discusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing. ESD Testing: From Components to Systems is part of the authors series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.

Textauszug

Chapter 1
Introduction

1.1 Testing for ESD, EMI, EOS, EMC, and Latchup

In the electronics industry, testing of components and systems is a part of the process of qualifying and releasing products. Standards are established to provide methodology, process, and guidance to quantify the technology issue [1–14]. Testing is performed to evaluate the sensitivity and susceptibility of products to electric, magnetic, and electromagnetic events. These can be categorized into electrostatic discharge (ESD) [1–12], electrical overstress (EOS), electromagnetic interference (EMI), and electromagnetic compatibility (EMC) events, and latchup (Figure 1.1) [13]. In the electronic industry, tests and procedures have been established to quantify the influence of these events on components and systems associated with ESD, EOS, EMC, and latchup [15–24].

Figure 1.1 ESD, EMI, EOS, and EMC

1.2 Component and System Level Testing

In the testing of electronics, different tests and procedures were established that tested components, and other tests for testing of systems. These tests have been established based on the environment that the components and systems experience in processing, assembly, shipping, to product use [1–24].

Figure 1.2 shows examples of component tests that are applied to wafer level, packaged and unpackaged products. Today, it is common to test semiconductor components for the following standards. These include the human body model (HBM) [1], machine model (MM) [2, 3], charged device model (CDM) [4, 5], to transmission line pulse (TLP) [6, 7], and very fast transmission line pulse (VF-TLP) [8, 9]. In the future chapters, these tests are discussed in depth.

Figure 1.2 Component tests

Figure 1.3 shows examples of system level tests that are applied to systems to address the robustness to environments that the systems may experience in product use. For system level tests, it is now common to test for the IEC 61000-4-2 [10], human metal model (HMM) [11], IEC 61000-4-5 [12], and cable discharge events (CDE).

Figure 1.3 System level tests

1.3 Qualification Testing

Many of the tests are used for different purposes. Some electrical tests are established for characterization, whereas other tests have been established for qualification of components or systems. Qualification tests are performed to guarantee or insure quality and reliability in the system, or in the field. Figure 1.4 shows examples of qualification tests that are performed in the electronic industry. These qualification tests include standard practice (SP) documents, to standard test method (STM).

Figure 1.4 Qualification testing

1.4 ESD Standards

In the development of these qualification processes, different types of documents and processes are established. In standards development, practices and processes are established for the quality, reliability, and release of products to customers.

1.4.1 Standard Development – Standard Practice (SP) and Standard Test Methods (STMs)

In the development of these qualification processes, a standard practice is established for testing of components and systems. A standard practice (SP) is a procedure or process that is established for testing. The document for the standard practice is called the standard practice (SP) document. A second practice is to establish an STM. The distinction between the standard practice (SP) and an STM is the STM procedure insures reproducibility and repeatability. In standards development, both standard practices (SP) and STM are established for the quality, reliability, and release of products to customers.

1.4.2 Repeatability

In STM development, repeatability is an important criterion in order to have a process elevate from a standard practice to an STM. It is important to know that if a test is performed, the experimental results are repeatable (Figure 1.5).

Figure 1.5 Repeatability and Reproducibility

1.4.3 Reproducibility

In STM development, reproducibility is a second important criterion in order to have a process elevate from a standard practice (SP) to an STM. Reproducibility is key to verify that the experimental results can be reproduced (Figure 1.6).

Figure 1.6 SP to STM Process

1.4.4 Round Robin Testing

In order to determine if a standard practice can be elevated to an STM, reproducibility and repeatability are evaluated in a process known as Round Robin (RR) process. Statistical analysis is initiated to determine the success or failure of reproducibility and repeatability as part of the experimental methodology. RR is an interlaboratory test that can include measurement, analysis or performing an experiment. This process can include a number of independent scientists and independent laboratories. In the case of ESD and EOS testing, different commercial test equipment is used in the process. To assess the measurement system, the statistics of analysis of variance (ANOVA) random effects model is used.

1.4.5 Round Robin Statistical Analysis – k-Statistics

In the RR process, the within-laboratory consistency statistics is known as the k-statistics. The k-statistics is the quotient of the laboratory standard deviation and the mean standard deviation of all the laboratories. These can be visualized using Mandel statistics and Mandel plots. Mandel's k is an indicator of the precision compared to the pooled standard deviation across all groups. Mandel's k plot is represented by a bar graph (Figure 1.7).

Figure 1.7 Mandel k-statistics plot

1.4.6 Round Robin Statistical Analysis – h-Statistics

In the RR process, the between-laboratory consistency statistics is known as the h-statistics. The h-statistics is the ratio of the difference between the laboratory mean and the mean of all the laboratories, and the standard deviation of the means from all the laboratories. These can be visualized using Mandel statistics and Mandel plots. Mandel's statistics are traditionally plotted for interlaboratory study data, grouped by laboratory to give a graphical view of laboratory bias and precision. Mandel's h-plots are bar graphs around a zero axis (Figure 1.8).

Figure 1.8 Mandel h-statistics plot

1.5 Component Level Standards

Today, in the semiconductor industry, components are tested to the HBM, MM, and CDM [1–5]. These tests are traditionally done on packaged components. In these tests, the components are also unpowered. For the qualification of semiconductor components for over 20 years, the HBM, MM, and CDM tests were completed prior to shipping components to a customer or system developer. In addition, latchup qualification was required in the shipping of components since the 1980s time frame [13]. A new test of components includes the HMM test to evaluate the influence of the components on system level tests.

In the 1990s, TLP testing became popular and is now a common characterization practice in the semiconductor industry. TLP testing did not have an established methodology until the year 2003 [6]. TLP testing is performed on test structures, circuits, to components. This was followed by a second test method known as the VF-TLP testing method [8]. VF-TLP testing is also completed on test structures to components. These TLP tests can also be performed on systems.

1.6 System Level Standards

System level standards are to address the sensitivity and susceptibility of electronic systems in shipping, handling, and usage environment. The objective is to simulate events that can occur. A distinction between many of the component standard tests and the system standards is the failure criteria. In system testing, the failure can be nondestructive and destructive. System level interrupts and disturbs can be regarded as a system failure.

System testing can be evaluated with all the modules of the system assembled or unassembled. System level testing can be with or without the cable connections between the system modules.

System level standards can include direct current (DC), alternating current (AC), pulse events, as well as transient phenomena. In the text, the system level tests known as IEC 61000-4-2 and IEC 61000-4-5 are discussed. In addition, CDE is discussed from charged cables.

1.7 Factory and Material Standards

In the semiconductor industry, there exist ESD and EOS standards for the factory and assembly environments [10]. ESD concerns in manufacturing are a combination of the materials, tooling, and the human factors. The materials influence the triboelectric charge transfer. The tooling used can lead to charge transfer, and operators can participate in this transfer process.

In the manufacturing area, the electric field between the ceiling and the floor is influenced by the height of the ceiling, air flow, and placement of the ionizers. The placement of the ionizers relative to the work surface where the sensitive parts are placed influences the effectiveness of the ionizers. The work surface material and its physical size is also a factor.

Operators in the manufacturing line can influence...

Produkt-Details

• Erscheint lt. Verlag: 14.10.2016
• Sprache: englisch
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Cable Discharge Event • Charged Device Model • Circuit Theory & Design • Components & Devices • Electrical & Electronics Engineering • Electrical Overstress • Electromagnetic Compatibility • Electrostatic Discharge testing • Elektrostatische Entladung • Elektrotechnik u. Elektronik • ESD testing • Halbleiter • Halbleiterbauelement • human body model • IEC 61000-4-2 Test • Komponenten u. Bauelemente • Schaltkreise - Theorie u. Entwurf • semiconductors • System Level Testing • TLP testing • Transmission Line Pulse testing • Very Fast Transmission Line Pulse • VF-TLP
• ISBN-13: 9781118707159 / 9781118707159