With the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance.
ESD Testing: From Components to Systems updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup.
Key features:
- Provides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5.
- Discusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP).
- Describes both conventional testing and new testing techniques for both chip and system level evaluation.
- Addresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods.
- Discusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing.
ESD Testing: From Components to Systems is part of the authors' series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.
Dr Steven H. Voldman, IEEE Fellow, Vermont, USA
Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for 'Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.' Voldman was a member of the semiconductor development of IBM for 25 years as well as a consultant for TSMC, and Samsung Electronics. Dr. Voldman initiated the first transmission line pulse (TLP) standard development team, and a participant in the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2013, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP. He initiated the 'ESD on Campus' program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China. Dr. Voldman teaches short courses and tutorials on ESD, latchup, patenting, and invention.
With the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance. ESD Testing: From Components to Systems updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup. Key features: Provides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5. Discusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP). Describes both conventional testing and new testing techniques for both chip and system level evaluation. Addresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods. Discusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing. ESD Testing: From Components to Systems is part of the authors series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.
Dr Steven H. Voldman, IEEE Fellow, Vermont, USA Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for "Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology." Voldman was a member of the semiconductor development of IBM for 25 years as well as a consultant for TSMC, and Samsung Electronics. Dr. Voldman initiated the first transmission line pulse (TLP) standard development team, and a participant in the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2013, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP. He initiated the "ESD on Campus" program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China. Dr. Voldman teaches short courses and tutorials on ESD, latchup, patenting, and invention.
Cover 1
Title Page 5
Copyright 6
Dedication 7
Contents 9
About the Author 19
Preface 21
Acknowledgments 25
Chapter 1 Introduction 27
1.1 Testing for ESD, EMI, EOS, EMC, and Latchup 27
1.2 Component and System Level Testing 27
1.3 Qualification Testing 28
1.4 ESD Standards 29
1.4.1 Standard Development-Standard Practice (SP) and Standard Test Methods (STMs) 29
1.4.2 Repeatability 30
1.4.3 Reproducibility 30
1.4.4 Round Robin Testing 30
1.4.5 Round Robin Statistical Analysis-k-Statistics 31
1.4.6 Round Robin Statistical Analysis-h-Statistics 32
1.5 Component Level Standards 32
1.6 System Level Standards 33
1.7 Factory and Material Standards 33
1.8 Characterization Testing 34
1.8.1 Semiconductor Component Level Characterization 35
1.8.2 Semiconductor Device Level Characterization 35
1.8.3 Wafer Level ESD Characterization Testing 35
1.8.4 Device Characterization Tests on Circuits 36
1.8.5 Device Characterization Tests on Components 36
1.8.6 System level Characterization on Components 37
1.8.7 Testing to Standard Specification Levels 37
1.8.8 Testing to Failure 37
1.9 ESD Library Characterization and Qualification 38
1.10 ESD Component Standards and Chip Architectures 38
1.10.1 Relationship Between ESD Standard Pin Combinations and Failure Mechanisms 38
1.10.2 Relationship Between ESD Standard Pin Combinations and Chip Architecture 39
1.11 System Level Characterization 39
1.12 Summary and Closing Comments 39
Problems 40
References 41
Chapter 2 Human Body Model 43
2.1 History 43
2.2 Scope 44
2.3 Purpose 44
2.4 Pulse Waveform 44
2.5 Equivalent Circuit 45
2.6 Test Equipment 46
2.7 Test Sequence and Procedure 49
2.8 Failure Mechanisms 51
2.9 HBM ESD Current Paths 52
2.10 HBM ESD Protection Circuit Solutions 54
2.11 Alternate Test Methods 58
2.11.1 HBM Split Fixture Testing 58
2.11.2 HBM Sample Testing 59
2.11.3 HBM Wafer Level ESD Testing 59
2.11.4 HBM Test Extraction Across the Device Under Test (DUT) 59
2.12 HBM Two-Pin Stress 60
2.12.1 HBM Two-Pin Stress-Advantages 63
2.12.2 HBM Two-Pin Stress-Pin Combinations 63
2.13 HBM Small Step Stress 63
2.13.1 HBM Small Step Stress-Advantages 64
2.13.2 HBM Small Step Stress-Data Analysis Methods 64
2.13.3 HBM Small Step Stress-Design Optimization 64
2.14 Summary and Closing Comments 64
Problems 65
References 65
Chapter 3 Machine Model 69
3.1 History 69
3.2 Scope 69
3.3 Purpose 69
3.4 Pulse Waveform 70
3.4.1 Comparison of Machine Model (MM) and Human Body Model (HBM) Pulse Waveform 70
3.5 Equivalent Circuit 71
3.6 Test Equipment 71
3.7 Test Sequence and Procedure 73
3.8 Failure Mechanisms 75
3.9 MM ESD Current Paths 75
3.10 MM ESD Protection Circuit Solutions 78
3.11 Alternate Test Methods 81
3.11.1 Small Charge Model (SCM) 81
3.12 Machine Model to Human Body Model Ratio 83
3.13 Machine Model Status as an ESD Standard 84
3.14 Summary and Closing Comments 84
Problems 85
References 85
Chapter 4 Charged Device Model (CDM) 87
4.1 History 87
4.2 Scope 87
4.3 Purpose 88
4.4 Pulse Waveform 88
4.4.1 Charged Device Model Pulse Waveform 88
4.4.2 Comparison of Charged Device Model (CDM) and Human Body Model (HBM) Pulse Waveform 89
4.5 Equivalent Circuit 91
4.6 Test Equipment 91
4.7 Test Sequence and Procedure 93
4.8 Failure Mechanisms 95
4.9 CDM ESD Current Paths 96
4.10 CDM ESD Protection Circuit Solutions 98
4.11 Alternative Test Methods 100
4.11.1 Alternative Test Methods-Socketed Device Model (SDM) 100
4.12 Charged Board Model (CBM) 101
4.12.1 Comparison of Charged Board Model (CBM) and Charged Device Model (CDM) Pulse Waveform 101
4.12.2 Charged Board Model (CBM) as an ESD Standard 103
4.13 Summary and Closing Comments 103
Problems 105
References 106
Chapter 5 Transmission Line Pulse (TLP) Testing 110
5.1 History 110
5.2 Scope 111
5.3 Purpose 111
5.4 Pulse Waveform 112
5.5 Equivalent Circuit 113
5.6 Test Equipment 114
5.6.1 Current Source 116
5.6.2 Time Domain Reflection (TDR) 116
5.6.3 Time Domain Transmission (TDT) 117
5.6.4 Time Domain Reflection and Transmission (TDRT) 117
5.6.5 Commercial Transmission Line Pulse (TLP) Systems 118
5.7 Test Sequence and Procedure 121
5.7.1 TLP Pulse Analysis 122
5.7.2 Measurement Window 122
5.7.3 Measurement Analysis-TDR Voltage Waveform 122
5.7.4 Measurement Analysis-Time Domain Reflection (TDR) Current Waveform 123
5.7.5 Measurement Analysis-Time Domain Reflection (TDR) Current-Voltage Characteristic 124
5.8 TLP Pulsed I-V Characteristic 124
5.8.1 TLP I-V Characteristic Key Parameters 125
5.8.2 TLP Power Versus Time 125
5.8.3 TLP Power Versus Time-Measurement Analysis 126
5.8.4 TLP Power-to-Failure Versus Pulse Width Plot 126
5.9 Alternate Methods 127
5.9.1 Long Duration TLP (LD-TLP) 127
5.9.2 Long Duration TLP Time Domain 128
5.10 TLP-to-HBM Ratio 130
5.10.1 Comparison of Transmission Line Pulse (TLP) and Human Body Model (HBM) Pulse Width 130
5.11 Summary and Closing Comments 130
Problems 130
References 131
Chapter 6 Very Fast Transmission Line Pulse (VF-TLP) Testing 134
6.1 History 134
6.2 Scope 134
6.3 Purpose 134
6.4 Pulse Waveform 135
6.4.1 Comparison of VF-TLP Versus TLP Waveform 136
6.5 Equivalent Circuit 137
6.6 Test Equipment Configuration 137
6.6.1 Current Source 138
6.6.2 Time Domain Reflection (TDR) 138
6.6.3 Time Domain Transmission (TDT) 138
6.6.4 Time Domain Reflection and Transmission (TDRT) 139
6.6.5 Early VF-TLP Systems 140
6.6.6 Commercial VF-TLP Test Systems 142
6.7 Test Sequence and Procedure 143
6.7.1 VF-TLP Pulse Analysis 144
6.7.2 Measurement Window 144
6.7.3 Measurement Analysis-VF-TLP Voltage Waveform 144
6.7.4 Measurement Analysis-Time Domain Reflectometry (TDR) Current Waveform 144
6.7.5 Measurement Analysis-Time Domain Transmission (TDR) Current-Voltage Characteristics 145
6.8 VF-TLP Pulsed I-V Characteristics 147
6.8.1 VF-TLP Pulsed I-V Characteristic Key Parameters 147
6.8.2 VF-TLP Power Versus Time Plot 148
6.8.3 VF-TLP Power Versus Time-Measurement Analysis 149
6.8.4 VF-TLP Power-to-Failure Versus Pulse Width Plot 149
6.8.5 VF-TLP and TLP Power-to-Failure Plot 150
6.9 Alternate Test Methods 150
6.9.1 Radio Frequency (RF) VF-TLP Systems 150
6.9.2 Ultrafast Transmission Line Pulse (UF-TLP) 151
6.10 Summary and Closing Comments 151
Problems 154
References 154
Chapter 7 IEC 61000-4-2 156
7.1 History 156
7.2 Scope 156
7.3 Purpose 156
7.3.1 Air Discharge 157
7.3.2 Direct Contact Discharge 157
7.4 Pulse Waveform 157
7.4.1 Pulse Waveform Equation 158
7.5 Equivalent Circuit 159
7.6 Test Equipment 159
7.6.1 Test Configuration 160
7.6.2 ESD Guns 160
7.6.3 ESD Guns-Standard Versus Discharge Module 161
7.6.4 Human Body Model Versus IEC 61000-4-2 161
7.7 Test Sequence and Procedure 161
7.8 Failure Mechanisms 163
7.9 IEC 61000-4-2 ESD Current Paths 164
7.10 ESD Protection Circuitry Solutions 165
7.11 Alternative Test Methods 166
7.11.1 Automotive ESD Standards 167
7.11.2 Medical ESD Standards 168
7.11.3 Avionic ESD Standard 169
7.11.4 Military-Related ESD Standard 169
7.12 Summary and Closing Comments 169
Problems 169
References 170
Chapter 8 Human Metal Model (HMM) 173
8.1 History 173
8.2 Scope 173
8.3 Purpose 174
8.4 Pulse Waveform 174
8.4.1 Pulse Waveform Equation 174
8.5 Equivalent Circuit 175
8.6 Test Equipment 175
8.7 Test Configuration 176
8.7.1 Horizontal Configuration 177
8.7.2 Vertical Configuration 177
8.7.3 HMM Fixture Board 178
8.8 Test Sequence and Procedure 179
8.8.1 Current Waveform Verification 180
8.8.2 Current Probe Verification Methodology 180
8.8.3 Current Probe Waveform Comparison 182
8.9 Failure Mechanisms 183
8.10 ESD Current Paths 184
8.11 ESD Protection Circuit Solutions 184
8.12 Summary and Closing Comments 186
Problems 186
References 187
Chapter 9 IEC 61000-4-5 189
9.1 History 189
9.2 Scope 190
9.3 Purpose 190
9.4 Pulse Waveform 191
9.5 Equivalent Circuit 192
9.6 Test Equipment 192
9.7 Test Sequence and Procedure 194
9.8 Failure Mechanisms 194
9.9 IEC 61000-4-5 ESD Current Paths 196
9.10 ESD Protection Circuit Solutions 196
9.11 Alternate Test Methods 197
9.12 Summary and Closing Comments 197
Problems 198
References 198
Chapter 10 Cable Discharge Event (CDE) 200
10.1 History 200
10.2 Scope 201
10.3 Purpose 201
10.4 Cable Discharge Event-Charging, Discharging, and Pulse Waveform 201
10.4.1 Charging Process 202
10.4.2 Discharging Process 202
10.4.3 Pulse Waveform 202
10.4.4 Comparison of CDE and IEC 61000-4-2 Pulse Waveform 202
10.5 Equivalent Circuit 204
10.6 Test Equipment 205
10.6.1 Commercial Test Systems 205
10.7 Test Measurement 206
10.7.1 Measurement 206
10.7.2 Measurement -Transmission Line Test Generators 206
10.7.3 Measurement-Low-Impedance Transmission Line Waveform 207
10.7.4 Schematic Capturing System Response to Reference Waveform 208
10.7.5 Tapered Transmission Lines 211
10.7.6 ESD Current Sensor 211
10.8 Test Procedure 211
10.9 Measurement of a Cable in Different Conditions 211
10.9.1 Test System Configuration and Diagram 213
10.9.2 Cable Configurations-Handheld Cable 215
10.9.3 Cable Configuration-Taped to Ground Plane 217
10.9.4 Cable Configurations-Pulse Analysis Summary 217
10.10 Transient Field Measurements 221
10.10.1 Transient Field Measurement of Short-Length Cable Discharge Events 221
10.10.2 Antenna-Induced Voltages 221
10.11 Telecommunication Cable Discharge Test System 221
10.12 Cable Discharge Current Paths 226
10.13 Failure Mechanisms 226
10.13.1 Cable Discharge Event Failure-Connector Failure 226
10.13.2 Cable Discharge Event Failure-Printed Circuit Board 227
10.13.3 Cable Discharge Event Failure-Semiconductor On-Chip 227
10.13.4 Cable Discharge Event (CDE)-Induced Latchup 227
10.14 Cable Discharge Event (CDE) Protection 227
10.14.1 RJ-45 Connectors 228
10.14.2 Printed Circuit Board Design Considerations 228
10.14.3 ESD Circuitry 228
10.14.4 Cable Discharge Event (CDE) ESD Protection Validation 229
10.15 Alternative Test Methods 229
10.16 Summary and Closing Comments 230
Problems 230
References 230
Chapter 11 Latchup 232
11.1 History 232
11.2 Purpose 234
11.3 Scope 235
11.4 Pulse Waveform 235
11.5 Equivalent Circuit 235
11.6 Test Equipment 235
11.7 Test Sequence and Procedure 237
11.8 Failure Mechanisms 241
11.9 Latchup Current Paths 242
11.10 Latchup Protection Solutions 242
11.10.1 Latchup Protection Solutions-Semiconductor Process 245
11.10.2 Latchup Protection Solutions-Design Layout 245
11.10.3 Latchup Protection Solutions-Circuit Design 246
11.10.4 Latchup Protection Solutions-System Level Design 247
11.11 Alternate Test Methods 248
11.11.1 Photoemission Techniques-PICA-TLP 248
11.11.2 Photoemission Techniques-CCD Method 250
11.12 Single Event Latchup (SEL) Test Methods 250
11.13 Summary and Closing Comments 250
Problems 253
References 253
Chapter 12 Electrical Overstress (EOS) 256
12.1 History 256
12.2 Scope 258
12.3 Purpose 259
12.4 Pulse Waveform 259
12.5 Equivalent Circuit 259
12.6 Test Equipment 260
12.7 Test Procedure and Sequence 260
12.8 Failure Mechanisms 262
12.8.1 Information Gathering 262
12.8.2 Failure Verification 263
12.8.3 Failure Site Identification and Localization 263
12.8.4 Root Cause Determination 264
12.8.5 Feedback of Root Cause 264
12.8.6 Corrective Actions 264
12.8.7 Documentation Reports 264
12.8.8 Statistical Analysis, Record Retention, and Control 264
12.9 Electrical Overstress (EOS) Protection Circuit Solutions 266
12.10 Electrical Overstress (EOS) Testing-TLP Method and EOS 275
12.10.1 Electrical Overstress (EOS) Testing-Long Duration Transmission Line Pulse (LD-TLP) Method 276
12.10.2 Electrical Overstress (EOS) Testing-Transmission Line Pulse (TLP) Method, EOS, and the Wunsch-Bell Model 276
12.10.3 Electrical Overstress (EOS) Testing-Limitations of the Transmission Line Pulse (TLP) Method for the Evaluation of EOS for Systems 276
12.10.4 Electrical Overstress (EOS) Testing-Electromagnetic Pulse (EMP) 277
12.11 Electrical Overstress (EOS) Testing-DC and Transient Latchup Testing 278
12.12 Summary and Closing Comments 278
Problems 278
References 279
Chapter 13 Electromagnetic Compatibility (EMC) 283
13.1 History 283
13.2 Purpose 284
13.3 Scope 284
13.4 Pulse Waveform 284
13.5 Equivalent Circuit 285
13.6 Test Equipment 285
13.6.1 Commercial Test System 285
13.6.2 Scanning Systems 286
13.7 Test Procedures 287
13.7.1 ESD/EMC Scanning Test Procedure and Method 287
13.8 Failure Mechanisms 287
13.9 ESD/EMC Current Paths 289
13.10 EMC Solutions 290
13.11 Alternative Test Methods 292
13.11.1 Scanning Methodologies 292
13.11.2 Testing-Susceptibility and Vulnerability 292
13.11.3 EMC/ESD Scanning-Semiconductor Component and Populated Printed Circuit Board 293
13.12 EMC/ESD Product Evaluation-IC Prequalification 293
13.13 EMC/ESD Scanning Detection-Upset Evaluation 293
13.13.1 ESD/EMC Scanning Stimulus 293
13.14 EMC/ESD Product Qualification Process 294
13.14.1 EMC/ESD Reproducibility 294
13.14.2 EMC/ESD Failure Threshold Mapping and Histogram 294
13.14.3 ESD Immunity Test-IC Level 294
13.14.4 ESD Immunity Test-ATE Stage 297
13.15 Alternative ESD/EMC Scanning Methods 297
13.15.1 Alternative ESD/EMC Scanning Methods-Printed Circuit Board 297
13.15.2 Electromagnetic Interference (EMI) Emission Scanning Methodology 300
13.15.3 Radio Frequency (RF) Immunity Scanning Methodology 300
13.15.4 Resonance Scanning Methodology 301
13.15.5 Current Spreading Scanning Methodology 301
13.16 Current Reconstruction Methodology 302
13.16.1 EOS and Residual Current 302
13.16.2 Printed Circuit Board (PCB) Trace Electromagnetic Emissions 302
13.16.3 Test Procedure and Sequence 303
13.17 Printed Circuit Board (PCB) Design EMC Solutions 303
13.18 Summary and Closing Comments 306
Problems 307
References 308
Appendix A Glossary of Terms 310
Appendix B Standards 314
B.1 ESD Association 314
B.2 International Organization of Standards 315
B.3 IEC 315
B.4 RTCA 315
B.5 Department of Defense 315
B.6 Military Standards 315
B.7 Airborne Standards and Lightning 316
Index 317
EULA 324
| Erscheint lt. Verlag | 7.10.2016 |
|---|---|
| Sprache | englisch |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| Schlagworte | Cable Discharge Event • Charged Device Model • Circuit Theory & Design • Components & Devices • Electrical & Electronics Engineering • Electrical Overstress • Electromagnetic Compatibility • Electrostatic Discharge testing • Elektrostatische Entladung • Elektrotechnik u. Elektronik • ESD testing • Halbleiter • Halbleiterbauelement • human body model • IEC 61000-4-2 Test • Komponenten u. Bauelemente • Schaltkreise - Theorie u. Entwurf • semiconductors • System Level Testing • TLP testing • Transmission Line Pulse testing • Very Fast Transmission Line Pulse • VF-TLP |
| ISBN-13 | 9781118707142 / 9781118707142 |
| Informationen gemäß Produktsicherheitsverordnung (GPSR) | |
| Haben Sie eine Frage zum Produkt? |
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