High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture
Springer Verlag, Singapore
978-981-97-3476-4 (ISBN)
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For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time.
This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices.
Jinshan Yue received the B.S. and Ph.D. degrees from the Electronic Engineering Department, Tsinghua University, Beijing, China, in 2016 and 2021, respectively. He is currently a post-doctor and research assistant at the Institute of Microelectronics of the Chinese Academy of Sciences. His current research interests include energy-efficient neural network processor, non-volatile memory, and computing-in-memory system design. He has authored and co-authored over 60 technical papers. He has received the excellent doctoral dissertation of Tsinghua University, ASP-DAC2021 Student Research Forum Best Poster Award, and 2021 Beijing Nova Program.
Introduction.- Basis and research status of neural network processor.- Neural network processor for specific kernel optimized data reuse.- Neural network processor with frequency domain compression algorithm optimization.- Neural network processor combining digital and computing in memory architecture.- Digital computing in memory neural network processor supporting large scale models.- Conclusion and prospect.
| Erscheinungsdatum | 03.08.2024 |
|---|---|
| Reihe/Serie | Springer Theses |
| Zusatzinfo | 78 Illustrations, color; 3 Illustrations, black and white |
| Verlagsort | Singapore |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Informatik ► Theorie / Studium ► Künstliche Intelligenz / Robotik |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | Application Specific Integrated Circuits • Computing-in-Memory • High Energy Efficiency • Neural Network Processor • System on chip |
| ISBN-10 | 981-97-3476-2 / 9819734762 |
| ISBN-13 | 978-981-97-3476-4 / 9789819734764 |
| Zustand | Neuware |
| Informationen gemäß Produktsicherheitsverordnung (GPSR) | |
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