FPGA-based Implementation of Signal Processing Systems (eBook)

Roger Woods, John McAllister, Gaye Lightbody, Ying Yi (Autoren)

eBook Download: PDF

2017 | 2. Auflage
John Wiley & Sons (Verlag)
978-1-119-07797-8 (ISBN)

Infos

An important working resource for engineers and researchers involved in the design, development, and implementation of signal processing systems

The last decade has seen a rapid expansion of the use of field programmable gate arrays (FPGAs) for a wide range of applications beyond traditional digital signal processing (DSP) systems. Written by a team of experts working at the leading edge of FPGA research and development, this second edition of FPGA-based Implementation of Signal Processing Systems has been extensively updated and revised to reflect the latest iterations of FPGA theory, applications, and technology. Written from a system-level perspective, it features expert discussions of contemporary methods and tools used in the design, optimization and implementation of DSP systems using programmable FPGA hardware. And it provides a wealth of practical insights-along with illustrative case studies and timely real-world examples-of critical concern to engineers working in the design and development of DSP systems for radio, telecommunications, audio-visual, and security applications, as well as bioinformatics, Big Data applications, and more. Inside you will find up-to-date coverage of:

• FPGA solutions for Big Data Applications, especially as they apply to huge data sets
• The use of ARM processors in FPGAs and the transfer of FPGAs towards heterogeneous computing platforms
• The evolution of High Level Synthesis tools-including new sections on Xilinx's HLS Vivado tool flow and Altera's OpenCL approach
• Developments in Graphical Processing Units (GPUs), which are rapidly replacing more traditional DSP systems

FPGA-based Implementation of Signal Processing Systems, 2nd Edition is an indispensable guide for engineers and researchers involved in the design and development of both traditional and cutting-edge data and signal processing systems. Senior-level electrical and computer engineering graduates studying signal processing or digital signal processing also will find this volume of great interest.

Roger Woods is a full professor and Research Director for the Electronics and Computer Engineering Cluster at Queen's University Belfast, Northern Ireland, UK.
John McAllister is an academic at Queen's University Belfast, Northern Ireland, UK.
Gaye Lightbody is a Lecturer within the School of Computing and Mathematics at Ulster University, Northern Ireland, UK.
Ying Yi is currently a Senior Software Engineer at SN Systems, a wholly owned subsidiary of Sony Interactive Entertainment Inc, England, UK.

Inhalt

FPGA-based Implementation of Signal Processing Systems 3
Contents 9
Preface 17
List of Abbreviations 23
1 Introduction to Field Programmable Gate Arrays 29
1.1 Introduction 29
1.2 Field Programmable Gate Arrays 30
1.2.1 Rise of Heterogeneous Computing Platforms 32
1.2.2 Programmability and DSP 33
1.3 Influence of Programmability 34
1.4 Challenges of FPGAs 36
Bibliography 37
2 DSP Basics 39
2.1 Introduction 39
2.2 Definition of DSP Systems 40
2.2.1 Sampling 42
2.2.2 Sampling Rate 42
2.3 DSP Transformations 44
2.3.1 Discrete Fourier Transform 44
2.3.2 Fast Fourier Transform 45
2.3.3 Discrete Cosine Transform 46
2.3.4 Wavelet Transform 47
2.4 Filters 48
2.4.1 Finite Impulse Response Filter 48
2.4.2 Infinite Impulse Response Filter 52
2.4.3 Wave Digital Filters 53
2.5 Adaptive Filtering 57
2.5.1 Applications of Adaptive Filters 58
2.5.2 Adaptive Algorithms 58
2.5.3 LMS Algorithm 59
2.5.4 RLS Algorithm 60
2.5.5 Squared Givens Rotations 64
2.6 Final Comments 66
Bibliography 66
3 Arithmetic Basics 69
3.1 Introduction 69
3.2 Number Representations 70
3.2.1 Signed Magnitude 71
3.2.2 One’s Complement 71
3.2.3 Two’s Complement 72
3.2.4 Binary Coded Decimal 72
3.2.5 Fixed-Point Representation 73
3.2.6 Floating-Point Representation 74
3.3 Arithmetic Operations 75
3.3.1 Adders 75
3.3.2 Adders and Subtracters 77
3.3.3 Adder Final Remarks 79
3.3.4 Multipliers 79
3.4 Alternative Number Representations 83
3.4.1 Signed Digit Number Representation 83
3.4.2 Logarithmic Number Systems 84
3.4.3 Residue Number Systems 85
3.4.4 CORDIC 86
3.5 Division 87
3.5.1 Recurrence Division 87
3.5.2 Division by Functional Iteration 88
3.6 Square Root 88
3.6.1 Digit Recurrence Square Root 89
3.6.2 Square Root by Functional Iteration 89
3.6.3 Initial Approximation Techniques 90
3.7 Fixed-Point versus Floating-Point 92
3.7.1 Floating-Point on FPGA 93
3.8 Conclusions 94
Bibliography 95
4 Technology Review 98
4.1 Introduction 98
4.2 Implications of Technology Scaling 99
4.3 Architecture and Programmability 100
4.4 DSP Functionality Characteristics 102
4.4.1 Computational Complexity 102
4.4.2 Parallelism 103
4.4.3 Data Independence 103
4.4.4 Arithmetic Requirements 104
4.4.5 Processor Classification 104
4.5 Microprocessors 104
4.5.1 ARM Microprocessor Architecture Family 106
4.5.2 Parallella Computer 108
4.6 DSP Processors 110
4.6.1 Evolutions in DSP Microprocessors 111
4.6.2 TMS320C6678 Multicore DSP 113
4.7 Graphical Processing Units 114
4.7.1 GPU Architecture 115
4.8 System-on-Chip Solutions 116
4.8.1 Systolic Arrays 117
4.9 Heterogeneous Computing Platforms 119
4.10 Conclusions 120
Bibliography 120
5 Current FPGA Technologies 122
5.1 Introduction 122
5.2 Toward FPGAs 123
5.2.1 Early FPGA Architectures 125
5.3 Altera Stratix® V and 10 FPGA Family 126
5.3.1 ALMs 127
5.3.2 Memory Organization 128
5.3.3 DSP Processing Blocks 129
5.3.4 Clocks and Interconnect 131
5.3.5 Stratix® 10 innovations 131
5.4 Xilinx Ultrascale™/Virtex-7 FPGA Families 131
5.4.1 Configurable Logic Block 132
5.4.2 Memory 133
5.4.3 Digital Signal Processing 134
5.5 Xilinx Zynq FPGA Family 135
5.6 Lattice iCE40isp FPGA Family 136
5.6.1 Programmable Logic Blocks 137
5.6.2 Memory 138
5.6.3 Digital Signal Processing 138
5.7 MicroSemi RTG4 FPGA Family 139
5.7.1 Programmable Logic Blocks 139
5.7.2 Memory 139
5.7.3 Mathblocks for DSP 140
5.8 Design Stratregies for FPGA-based DSP Systems 140
5.8.1 DSP Processing Elements 140
5.8.2 Memory Organization 141
5.8.3 Other FPGA-Based Design Guidelines 141
5.9 Conclusions 142
Bibliography 142
6 Detailed FPGA Implementation Techniques 144
6.1 Introduction 144
6.2 FPGA Functionality 145
6.2.1 LUT Functionality 145
6.2.2 DSP Processing Elements 148
6.2.3 Memory Availability 149
6.3 Mapping to LUT-Based FPGA Technology 151
6.3.1 Reductions in Inputs/Outputs 151
6.3.2 Controller Design 153
6.4 Fixed-Coefficient DSP 153
6.4.1 Fixed-Coefficient FIR Filtering 154
6.4.2 DSP Transforms 155
6.4.3 Fixed-Coefficient FPGA Techniques 158
6.5 Distributed Arithmetic 158
6.5.1 DA Expansion 158
6.5.2 DA Applied to FPGA 160
6.6 Reduced-Coefficient Multiplier 161
6.6.1 DCT Example 162
6.6.2 RCM Design Procedure 162
6.6.3 FPGA Multiplier Summary 165
6.7 Conclusions 165
Bibliography 166
7 Synthesis Tools for FPGAs 168
7.1 Introduction 168
7.2 High-Level Synthesis 169
7.2.1 HLS from C-Based Languages 171
7.3 Xilinx Vivado 171
7.4 Control Logic Extraction Phase Example 172
7.5 Altera SDK for OpenCL 173
7.6 Other HLS Tools 175
7.6.1 Catapult 175
7.6.2 Impulse-C 175
7.6.3 GAUT 176
7.6.4 CAL 176
7.6.5 LegUp 178
7.7 Conclusions 178
Bibliography 178
8 Architecture Derivation for FPGA-based DSP Systems 180
8.1 Introduction 180
8.2 DSP Algorithm Characteristics 181
8.2.1 Further Characterization 182
8.3 DSP Algorithm Representations 185
8.3.1 SFG Descriptions 186
8.3.2 DFG Descriptions 186
8.4 Pipelining DSP Systems 188
8.4.1 Retiming 188
8.4.2 Cut-Set Theorem 191
8.4.3 Application of Delay Scaling 192
8.4.4 Calculation of Pipelining Period 195
8.4.5 Longest Path Matrix Algorithm 195
8.5 Parallel Operation 198
8.5.1 Unfolding 201
8.5.2 Folding 202
8.6 Conclusions 206
Bibliography 207
9 Complex DSP Core Design for FPGA 208
9.1 Introduction 208
9.2 Motivation for Design for Reuse 209
9.3 Intellectual Property Cores 210
9.4 Evolution of IP Cores 212
9.4.1 Arithmetic Libraries 213
9.4.2 Complex DSP Functions 215
9.4.3 Future of IP Cores 215
9.5 Parameterizable (Soft) IP Cores 215
9.5.1 Identifying Design Components Suitable for Development as IP 217
9.5.2 Identifying Parameters for IP Cores 218
9.5.3 Development of Parameterizable Features 221
9.5.4 Parameterizable Control Circuitry 222
9.5.5 Application to Simple FIR Filter 222
9.6 IP Core Integration 223
9.6.1 Design Issues 224
9.7 Current FPGA-based IP Cores 225
9.8 Watermarking IP 226
9.9 Summary 226
Bibliography 227
10 Advanced Model-Based FPGA Accelerator Design 228
10.1 Introduction 228
10.2 Dataflow Modeling of DSP Systems 229
10.2.1 Process Networks 229
10.2.2 Synchronous Dataflow 230
10.2.3 Cyclo-static Dataflow 231
10.2.4 Multidimensional Synchronous Dataflow 232
10.3 Architectural Synthesis of Custom Circuit Accelerators from DFGs 232
10.4 Model-Based Development of Multi-Channel Dataflow Accelerators 233
10.4.1 Multidimensional Arrayed Dataflow 235
10.4.2 Block and Interleaved Processing in MADF 237
10.4.3 MADF Accelerators 237
10.4.4 Pipelined FE Derivation for MADF Accelerators 238
10.4.5 WBC Configuration 241
10.4.6 Design Example: Normalized Lattice Filter 242
10.4.7 Design Example: Fixed Beamformer System 244
10.5 Model-Based Development for Memory-Intensive Accelerators 247
10.5.1 Synchronous Dataflow Representation of FSME 247
10.5.2 Cyclo-static Representation of FSME 249
10.6 Summary 251
References 251
11 Adaptive Beamformer Example 253
11.1 Introduction to Adaptive Beamforming 254
11.2 Generic Design Process 254
11.2.1 Adaptive Beamforming Specification 257
11.2.2 Algorithm Development 258
11.3 Algorithm to Architecture 259
11.3.1 Dependence Graph 260
11.3.2 Signal Flow Graph 261
11.4 Efficient Architecture Design 263
11.4.1 Scheduling the QR Operations 267
11.5 Generic QR Architecture 268
11.5.1 Processor Array 270
11.6 Retiming the Generic Architecture 274
11.6.1 Retiming QR Architectures 278
11.7 Parameterizable QR Architecture 281
11.7.1 Choice of Architecture 282
11.7.2 Parameterizable Control 284
11.7.3 Linear Architecture 284
11.7.4 Sparse Linear Architecture 286
11.7.5 Rectangular Architecture 290
11.7.6 Sparse Rectangular Architecture 292
11.7.7 Generic QR Cells 292
11.8 Generic Control 294
11.8.1 Generic Input Control for Linear and Sparse Linear Arrays 294
11.8.2 Generic Input Control for Rectangular and Sparse Rectangular Arrays 295
11.8.3 Effect of Latency on the Control Seeds 296
11.9 Beamformer Design Example 297
11.10 Summary 299
References 299
12 FPGA Solutions for Big Data Applications 301
12.1 Introduction 301
12.2 Big Data 302
12.3 Big Data Analytics 303
12.3.1 Inductive Learning 304
12.3.2 DataMining Algorithms 305
12.3.3 Classification 305
12.3.4 Regression 306
12.3.5 Clustering 307
12.3.6 The Right Approach 307
12.4 Acceleration 308
12.4.1 Scaling Up or Scaling Out 308
12.4.2 FPGA-based System Developments 309
12.4.3 FPGA Implementations 309
12.4.4 Heston Model Acceleration Using FPGA 310
12.5 k-Means Clustering FPGA Implementation 311
12.5.1 Computational Complexity Analysis of k-Means Algorithm 313
12.6 FPGA-Based Soft Processors 314
12.6.1 IPPro FPGA-Based Processor 315
12.7 System Hardware 318
12.7.1 Distance Calculation Block 319
12.7.2 Comparison Block 320
12.7.3 Averaging 320
12.7.4 Optimizations 320
12.8 Conclusions 321
Bibliography 321
13 Low-Power FPGA Implementation 324
13.1 Introduction 324
13.2 Sources of Power Consumption 325
13.2.1 Dynamic Power Consumption 325
13.2.2 Static power consumption 327
13.3 FPGA Power Consumption 328
13.3.1 Clock Tree Isolation 330
13.4 Power Consumption Reduction Techniques 330
13.5 Dynamic Voltage Scaling in FPGAs 331
13.6 Reduction in Switched Capacitance 333
13.6.1 Data Reordering 333
13.6.2 Pipelining 334
13.6.3 Locality 339
13.6.4 Data Mapping 341
13.7 Final Comments 344
Bibliography 345
14 Conclusions 347
14.1 Introduction 347
14.2 Evolution in FPGA Design Approaches 348
14.3 Big Data and the Shift toward Computing 348
14.4 Programming Flow for FPGAs 349
14.5 Support for Floating-Point Arithmetic 350
14.6 Memory Architectures 350
Bibliography 351
Index 353
EULA 359

Produkt-Details

• Erscheint lt. Verlag: 6.2.2017
• Sprache: englisch
• Themenwelt: Informatik ► Weitere Themen ► Hardware
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Nachrichtentechnik
• Schlagworte: applying acceleration using FPGAs • Circuit Theory & Design / VLSI / ULSI • Computer Science • Database & Data Warehousing Technologies • Datenbanken u. Data Warehousing • digital signal processing • Digital signal processing systems • digital signal processing systems development • digital signal process systems design • DSP • DSP systems design • DSP systems development • Electrical & Electronics Engineering • Elektrotechnik u. Elektronik • field programmable gate array hardware • field programmable gate array hardware for digital signal processing • field programmable gate arrays • FPGA applications • FPGA-based implementations for digital signal processing • FPGA-based implementations for Signal Processing • FPGA Big Data applications • FPGA Big Data applications for bioinformatics data sets • FPGA Big Data applications for oil and gas data sets • FPGA big data collation and analysis • FPGA Design • FPGA hardware in DSP • FPGAs • FPGAs applications for petroleum industry • FPGAs applications in bioinformatics • FPGAs for very large data sets • FPGAs in sensor arrays • FPGAs in telecommunications systems • FPGA theory • Informatik • programmable digital signal processing systems • programmable signal processing systems • Schaltkreise - Theorie u. Entwurf / VLSI / ULSI • Signal Processing • Signal Processing Systems • Signalverarbeitung • waves and wave mechanics
• ISBN-10: 1-119-07797-4 / 1119077974
• ISBN-13: 978-1-119-07797-8 / 9781119077978