VLSI Test Principles and Architectures (eBook)

Design for Testability

Laung-Terng Wang, Xiaoqing Wen, Cheng-Wen Wu (Autoren)

eBook Download: PDF

2006 | 1. Auflage
808 Seiten
Elsevier Science (Verlag)
978-0-08-047479-3 (ISBN)

Infos

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
· Most up-to-date coverage of design for testability.
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

Inhalt

Front cover 1
Title page 6
Copyright page 7
Table of contents 8
Preface 22
In the Classroom 25
Acknowledgments 26
Contributors 28
About the Editors 30
1 Introduction 32
Importance of Testing 32
Testing During the VLSI Lifecycle 33
VLSI Development Process 34
Design Verification 35
Yield and Reject Rate 36
Electronic System Manufacturing Process 37
System-Level Operation 37
Challenges in VLSI Testing 39
Test Generation 40
Fault Models 42
Stuck-At Faults 43
Transistor Faults 46
Open and Short Faults 47
Delay Faults and Crosstalk 50
Pattern Sensitivity and Coupling Faults 51
Analog Fault Models 52
Levels of Abstraction in VLSI Testing 53
Register-Transfer Level and Behavioral Level 53
Gate Level 54
Switch Level 55
Physical Level 55
Historical Review of VLSI Test Technology 56
Automatic Test Equipment 56
Automatic Test Pattern Generation 58
Fault Simulation 59
Digital Circuit Testing 59
Analog and Mixed-Signal Circuit Testing 60
Design for Testability 60
Board Testing 62
Boundary Scan Testing 63
Concluding Remarks 64
Exercises 64
Acknowledgments 65
References 65
2 Design for Testability 68
Introduction 68
Testability Analysis 71
SCOAP Testability Analysis 72
Combinational Controllability and Observability Calculation 72
Sequential Controllability and Observability Calculation 74
Probability-Based Testability Analysis 76
Simulation-Based Testability Analysis 78
RTL Testability Analysis 79
Design for Testability Basics 81
Ad Hoc Approach 82
Test Point Insertion 82
Structured Approach 84
Scan Cell Designs 86
Muxed-D Scan Cell 86
Clocked-Scan Cell 87
LSSD Scan Cell 88
Scan Architectures 90
Full-Scan Design 90
Muxed-D Full-Scan Design 90
Clocked Full-Scan Design 93
LSSD Full-Scan Design 93
Partial-Scan Design 95
Random-Access Scan Design 98
Scan Design Rules 101
Tristate Buses 102
Bidirectional I/O Ports 102
Gated Clocks 102
Derived Clocks 105
Combinational Feedback Loops 105
Asynchronous Set/Reset Signals 106
Scan Design Flow 107
Scan Design Rule Checking and Repair 108
Scan Synthesis 109
Scan Configuration 110
Scan Replacement 113
Scan Reordering 113
Scan Stitching 114
Scan Extraction 114
Scan Verification 115
Verifying the Scan Shift Operation 116
Verifying the Scan Capture Operation 117
Scan Design Costs 117
Special-Purpose Scan Designs 118
Enhanced Scan 118
Snapshot Scan 119
Error-Resilient Scan 121
RTL Design for Testability 123
RTL Scan Design Rule Checking and Repair 124
RTL Scan Synthesis 125
RTL Scan Extraction and Scan Verification 126
Concluding Remarks 126
Exercises 127
Acknowledgments 130
References 130
3 Logic and Fault Simulation 136
Introduction 137
Logic Simulation for Design Verification 137
Fault Simulation for Test and Diagnosis 138
Simulation Models 139
Gate-Level Network 140
Sequential Circuits 140
Logic Symbols 141
Unknown State u 142
High-Impedance State Z 144
Intermediate Logic States 145
Logic Element Evaluation 145
Truth Tables 146
Input Scanning 146
Input Counting 147
Parallel Gate Evaluation 147
Timing Models 149
Transport Delay 149
Inertial Delay 150
Wire Delay 150
Functional Element Delay Model 151
Logic Simulation 152
Compiled-Code Simulation 152
Logic Optimization 152
Logic Levelization 154
Code Generation 155
Event-Driven Simulation 156
Nominal-Delay Event-Driven Simulation 157
Compiled-Code Versus Event-Driven Simulation 160
Hazards 161
Static Hazard Detection 162
Dynamic Hazard Detection 163
Fault Simulation 163
Serial Fault Simulation 164
Parallel Fault Simulation 166
Parallel Fault Simulation 166
Parallel-Pattern Fault Simulation 168
Deductive Fault Simulation 170
Concurrent Fault Simulation 174
Differential Fault Simulation 177
Fault Detection 179
Comparison of Fault Simulation Techniques 180
Alternatives to Fault Simulation 182
Toggle Coverage 182
Fault Sampling 182
Critical Path Tracing 183
Statistical Fault Analysis 184
Concluding Remarks 185
Exercises 186
References 189
4 Test Generation 192
Introduction 192
Random Test Generation 194
Exhaustive Testing 197
Theoretical Background: Boolean Difference 197
Untestable Faults 199
Designing a Stuck-At ATPG for Combinational Circuits 200
A Naive ATPG Algorithm 200
Backtracking 203
A Basic ATPG Algorithm 204
D Algorithm 208
PODEM 213
FAN 217
Static Logic Implications 218
Dynamic Logic Implications 222
Designing a Sequential ATPG 225
Time Frame Expansion 225
5-Valued Algebra Is Insufficient 227
Gated Clocks and Multiple Clocks 228
Untestable Fault Identification 231
Multiple-Line Conflict Analysis 234
Designing a Simulation-Based ATPG 238
Overview 239
Genetic-Algorithm-Based ATPG 239
Issues Concerning the GA Population 243
Issues Concerning GA Parameters 244
Issues Concerning the Fitness Function 244
CASE Studies 246
Advanced Simulation-Based ATPG 249
Seeding the GA with Helpful Sequences 249
Logic-Simulation-Based ATPG 253
Spectrum-Based ATPG 256
Hybrid Deterministic and Simulation-Based ATPG 257
ALT-TEST Hybrid 259
ATPG for Non-Stuck-At Faults 262
Designing an ATPG That Captures Delay Defects 262
Classification of Path-Delay Faults 264
ATPG for Path-Delay Faults 267
ATPG for Transition Faults 269
Transition ATPG Using Stuck-At ATPG 271
Transition ATPG Using Stuck-At Vectors 271
Transition Test Chains via Weighted Transition Graph 272
Bridging Fault ATPG 275
Other Topics in Test Generation 277
Test Set Compaction 277
N-Detect ATPG 278
ATPG for Acyclic Sequential Circuits 278
IDDQ Testing 278
Designing a High-Level ATPG 279
Concluding Remarks 279
Exercises 280
References 287
5 Logic Built-In Self-Test 294
Introduction 295
BIST Design Rules 297
Unknown Source Blocking 298
Analog Blocks 298
Memories and Non-Scan Storage Elements 299
Combinational Feedback Loops 299
Asynchronous Set/Reset Signals 299
Tristate Buses 300
False Paths 301
Critical Paths 301
Multiple-Cycle Paths 301
Floating Ports 301
Bidirectional I/O Ports 302
Re-Timing 302
Test Pattern Generation 302
Exhaustive Testing 306
Binary Counter 306
Complete LFSR 306
Pseudo-Random Testing 308
Maximum-Length LFSR 309
Weighted LFSR 309
Cellular Automata 309
Pseudo-Exhaustive Testing 312
Verification Testing 313
Segmentation Testing 318
Delay Fault Testing 319
Summary 320
Output Response Analysis 321
Ones Count Testing 322
Transition Count Testing 322
Signature Analysis 323
Serial Signature Analysis 323
Parallel Signature Analysis 325
Logic BIST Architectures 327
BIST Architectures for Circuits without Scan Chains 327
A Centralized and Separate Board-Level BIST Architecture 327
Built-In Evaluation and Self-Test (BEST) 328
BIST Architectures for Circuits with Scan Chains 328
LSSD On-Chip Self-Test 328
Self-Testing Using MISR and Parallel SRSG 329
BIST Architectures Using Register Reconfiguration 329
Built-In Logic Block Observer 330
Modified Built-In Logic Block Observer 331
Concurrent Built-In Logic Block Observer 331
Circular Self-Test Path (CSTP) 333
BIST Architectures Using Concurrent Checking Circuits 334
Concurrent Self-Verification 334
Summary 335
Fault Coverage Enhancement 335
Test Point Insertion 336
Test Point Placement 337
Control Point Activation 338
Mixed-Mode BIST 339
ROM Compression 339
LFSR Reseeding 339
Embedding Deterministic Patterns 340
Hybrid BIST 340
BIST Timing Control 341
Single-Capture 341
One-Hot Single-Capture 341
Staggered Single-Capture 342
Skewed-Load 342
One-Hot Skewed-Load 343
Aligned Skewed-Load 343
Staggered Skewed-Load 345
Double-Capture 346
One-Hot Double-Capture 346
Aligned Double-Capture 347
Staggered Double-Capture 348
Fault Detection 348
A Design Practice 350
BIST Rule Checking and Violation Repair 351
Logic BIST System Design 351
Logic BIST Architecture 351
TPG and ORA 352
Test Controller 353
Clock Gating Block 354
Re-Timing Logic 356
Fault Coverage Enhancing Logic and Diagnostic Logic 356
RTL BIST Synthesis 357
Design Verification and Fault Coverage Enhancement 357
Concluding Remarks 358
Exercises 358
Acknowledgments 362
References 362
6 Test Compression 372
Introduction 373
Test Stimulus Compression 375
Code-Based Schemes 376
Dictionary Code (Fixed-to-Fixed) 376
Huffman Code (Fixed-to-Variable) 377
Run-Length Code (Variable-to-Fixed) 380
Golomb Code (Variable-to-Variable) 381
Linear-Decompression-Based Schemes 382
Combinational Linear Decompressors 386
Fixed-Length Sequential Linear Decompressors 386
Variable-Length Sequential Linear Decompressors . 387
Combined Linear and Nonlinear Decompressors 388
Broadcast-Scan-Based Schemes 390
Broadcast Scan 390
Illinois Scan 391
Multiple-Input Broadcast Scan 393
Reconfigurable Broadcast Scan 393
Virtual Scan 394
Test Response Compaction 395
Space Compaction 398
Zero-Aliasing Linear Compaction 398
X-Compact 400
X-Blocking 402
X-Masking 403
X-Impact 404
Time Compaction 405
Mixed Time and Space Compaction 406
Industry Practices 407
OPMISR+ 408
Embedded Deterministic Test 410
VirtualScan and UltraScan 413
Adaptive Scan 416
ETCompression 417
Summary 419
Concluding Remarks 419
Exercises 420
Acknowledgments 421
References 422
7 Logic Diagnosis 428
Introduction 428
Combinational Logic Diagnosis 432
Cause–Effect Analysis 432
Compaction and Compression of Fault Dictionary 434
Effect–Cause Analysis 436
Structural Pruning 438
Backtrace Algorithm 439
Inject-and-Evaluate Paradigm 440
Chip-Level Strategy 449
Direct Partitioning 449
Two-Phase Strategy 451
Overall Chip-Level Diagnostic Flow 455
Diagnostic Test Pattern Generation 456
Summary of Combinational Logic Diagnosis 457
Scan Chain Diagnosis 458
Preliminaries for Scan Chain Diagnosis 458
Hardware-Assisted Method 461
Modified Inject-and-Evaluate Paradigm 463
Signal-Profiling-Based Method 465
Diagnostic Test Sequence Selection 465
Run-and-Scan Test Application 465
Why Functional Sequence? 466
Profiling-Based Analysis 468
Summary of Scan Chain Diagnosis 472
Logic BIST Diagnosis 473
Overview of Logic BIST Diagnosis 473
Interval-Based Methods 474
Masking-Based Methods 477
Concluding Remarks 480
Exercises 481
Acknowledgments 484
References 485
8 Memory Testing and Built-In Self-Test 492
Introduction 493
RAM Functional Fault Models and Test Algorithms 494
RAM Functional Fault Models 494
RAM Dynamic Faults 496
Functional Test Patterns and Algorithms 497
March Tests 500
Comparison of RAM Test Patterns 502
Word-Oriented Memory 504
Multi-Port Memory 504
RAM Fault Simulation and Test Algorithm Generation 506
Fault Simulation 507
RAMSES 508
Test Algorithm Generation by Simulation 511
Memory Built-In Self-Test 519
RAM Specification and BIST Design Strategy 520
BIST Architectures and Functions 524
BIST Implementation 526
BRAINS: A RAM BIST Compiler 531
Concluding Remarks 539
Exercises 540
Acknowledgments 544
References 544
9 Memory Diagnosis and Built-In Self-Repair 548
Introduction 549
Why Memory Diagnosis? 549
Why Memory Repair? 549
Refined Fault Models and Diagnostic Test Algorithms 549
BIST with Diagnostic Support 552
Controller 552
Test Pattern Generator 554
Fault Site Indicator (FSI) 555
RAM Defect Diagnosis and Failure Analysis 557
RAM Redundancy Analysis Algorithms 560
Conventional Redundancy Analysis Algorithms 560
The Essential Spare Pivoting Algorithm 562
Repair Rate and Overhead 566
Built-In Self-Repair 568
Redundancy Organization 568
BISR Architecture and Procedure 569
BIST Module 572
BIRA Module 573
An Industrial Case 576
Repair Rate and Yield 579
Concluding Remarks 583
Exercises 583
Acknowledgments 584
References 584
10 Boundary Scan and Core-Based Testing 588
Introduction 589
IEEE 1149 Standard Family 589
Core-Based Design and Test Considerations 590
Digital Boundary Scan (IEEE Std. 1149.1) 592
Basic Concept 592
Overall 1149.1 Test Architecture and Operations 593
Test Access Port and Bus Protocols 595
Data Registers and Boundary-Scan Cells 596
TAP Controller 598
Instruction Register and Instruction Set 600
Boundary-Scan Description Language 605
On-Chip Test Support with Boundary Scan 605
Board and System-Level Boundary-Scan Control Architectures 607
Boundary Scan for Advanced Networks (IEEE 1149.6) 610
Rationale for 1149.6 610
1149.6 Analog Test Receiver 612
1149.6 Digital Driver Logic 612
1149.6 Digital Receiver Logic 613
1149.6 Test Access Port (TAP) 615
Summary 616
Embedded Core Test Standard (IEEE Std. 1500) 616
SOC (System-on-Chip) Test Problems 616
Overall Architecture 618
Wrapper Components and Functions 620
Instruction Set 628
Core Test Language (CTL) 632
Core Test Supporting and System Test Configurations 634
Hierarchical Test Control and Plug-and-Play 637
Comparisons between the 1500 and 1149.1 Standards 641
Concluding Remarks 642
Exercises 643
Acknowledgments 645
References 645
11 Analog and Mixed-Signal Testing 650
Introduction 650
Analog Circuit Properties 651
Continuous Signals 652
Large Range of Circuits 652
Nonlinear Characteristics 652
Feedback Ambiguity 653
Complicated Cause–Effect Relationship 653
Absence of Suitable Fault Model 653
Requirement for Accurate Instruments for Measuring Analog Signals 654
Analog Defect Mechanisms and Fault Models 654
Hard Faults 656
Soft Faults 656
Analog Circuit Testing 658
Analog Test Approaches 658
Analog Test Waveforms 660
DC Parametric Testing 662
Open-Loop Gain Measurement 663
Unit Gain Bandwidth Measurement 664
Common Mode Rejection Ratio Measurement 665
Power Supply Rejection Ratio Measurement 666
AC Parametric Testing 666
Maximal Output Amplitude Measurement 667
Frequency Response Measurement 668
SNR and Distortion Measurement 670
Intermodulation Distortion Measurement 672
Mixed-Signal Testing 672
Introduction to Analog–Digital Conversion 673
ADC and DAC Circuit Structure 675
DAC Circuit Structure 677
ADC Circuit Structure 677
ADC/DAC Specification and Fault Models 678
IEEE 1057 Standard 683
Time-Domain ADC Testing 685
Code Bins 685
Code Transition Level Test (Static) 686
Code Transition Level Test (Dynamic) 686
Gain and Offset Test 687
Linearity Error and Maximal Static Error 688
Sine Wave Curve-Fit Test 689
Frequency-Domain ADC Testing 689
IEEE 1149.4 Standard for a Mixed-Signal Test Bus 689
IEEE 1149.4 Overview 690
Scope of the Standard 691
IEEE 1149.4 Circuit Structures 692
IEEE 1149.4 Instructions 696
Mandatory Instructions 696
Optional Instructions 696
IEEE 1149.4 Test Modes 697
Open/Short Interconnect Testing 697
Extended Interconnect Measurement 698
Complex Network Measurement 702
High-Performance Configuration 703
Concluding Remarks 704
Exercises 704
Acknowledgments 707
References 708
12 Test Technology Trends in the Nanometer Age 710
Test Technology Roadmap 711
Delay Testing 716
Test Application Schemes for Testing Delay Defects 717
Delay Fault Models 718
Summary 721
Coping with Physical Failures, Soft Errors, and Reliability Issues 723
Signal Integrity and Power Supply Noise 723
Integrity Loss Fault Model 724
Location 725
Pattern Generation 725
Sensing and Readout 726
Parametric Defects, Process Variations, and Yield 727
Defect-Based Test 728
Soft Errors 729
Fault Tolerance 732
Defect and Error Tolerance 736
FPGA Testing 737
Impact of Programmability 737
Testing Approaches 739
Built-In Self-Test of Logic Resources 739
Built-In Self-Test of Routing Resources 740
Recent Trends 741
MEMS Testing 742
Basic Concepts for Capacitive MEMS Devices 742
MEMS Built-In Self-Test 744
Sensitivity BIST Scheme 744
Symmetry BIST Scheme 744
A Dual-Mode BIST Technique 745
A BIST Example for MEMS Comb Accelerometers 747
Conclusions 750
High-speed I/O Testing 750
I/O Interface Technology and Trend 751
I/O Testing and Challenges 755
High-Performance I/O Test Solutions 756
Future Challenges 757
RF Testing 759
Core RF Building Blocks 760
RF Test Specifications and Measurement Procedures 761
Gain 761
Conversion Gain 762
Third-Order Intercept 762
Noise Figure 764
Tests for System-Level Specifications 764
Adjacent Channel Power Ratio 764
Error Vector Magnitude, Magnitude Error, and Phase Error 765
Current and Future Trends 766
Future Trends 767
Concluding Remarks 768
Acknowledgments 769
References 769
Index 782

Produkt-Details

• Erscheint lt. Verlag: 14.8.2006
• Co-Autor: Michael S. Hsiao, Jiun-Lang Huang, Shi-Yu Huang, Wen-Ben Jone, Rohit Kapur, Brion Keller, Kuen-Jong Lee, James C.-M. Li, Mike Peng Li, Xiaowei Li, T.M. Mak, Yinghua Min, Benoit Nadeau-Dostie, Mehrdad Nourani, Janusz Rajski, Charles Stroud, Nur A. Touba, Erik H. Volkerink, Duncan M. (Hank) Walker, Shianling Wu, Khader S. Abdel-Hafez, Soumendu Bhattacharya, Abhijit Chatterjee, Xinghao Chen, Kwang-Ting (Tim) Cheng, William Eklow
• Sprache: englisch
• Themenwelt: Kunst / Musik / Theater ► Design / Innenarchitektur / Mode
• Themenwelt: Sachbuch/Ratgeber
• Themenwelt: Mathematik / Informatik ► Informatik
• Themenwelt: Technik ► Bauwesen
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Maschinenbau
• ISBN-10: 0-08-047479-9 / 0080474799
• ISBN-13: 978-0-08-047479-3 / 9780080474793