Finite State Machine Datapath Design, Optimization, and Implementation
Seiten
2007
Morgan & Claypool Publishers (Verlag)
978-1-59829-529-0 (ISBN)
Morgan & Claypool Publishers (Verlag)
978-1-59829-529-0 (ISBN)
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Explores the design space of combined FSM/Datapath implementations. The book begins by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail.
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.
Calculating Maximum Clock Frequency
Improving Design Performance
Finite State Machine with Datapath (FSMD) Design
Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs
| Erscheint lt. Verlag | 28.2.2008 |
|---|---|
| Reihe/Serie | Synthesis Lectures on Digital Circuits and Systems |
| Verlagsort | San Rafael |
| Sprache | englisch |
| Maße | 187 x 235 mm |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 1-59829-529-2 / 1598295292 |
| ISBN-13 | 978-1-59829-529-0 / 9781598295290 |
| Zustand | Neuware |
| Informationen gemäß Produktsicherheitsverordnung (GPSR) | |
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