SoC Physical Design (eBook)

A Comprehensive Guide

Veena S. Chakravarthi, Shivananda R. Koteshwar (Autoren)

eBook Download: PDF

2022
155 Seiten
Springer International Publishing (Verlag)
978-3-030-98112-9 (ISBN)

Infos

SoC Physical Design is a comprehensive practical guide for VLSI designers that thoroughly examines and explains the practical physical design flow of system on chip (SoC). The book covers the rationale behind making design decisions on power, performance, and area (PPA) goals for SoC and explains the required design environment algorithms, design flows, constraints, handoff procedures, and design infrastructure requirements in achieving them. The book reveals challenges likely to be faced at each design process and ways to address them in practical design environments. Advanced topics on 3D ICs, EDA trends, and SOC trends are discussed in later chapters. Coverage also includes advanced physical design techniques followed for deep submicron SOC designs. The book provides aspiring VLSI designers, practicing design engineers, and electrical engineering students with a solid background on the complex physical design requirements of SoCs which are required to contribute effectively in design roles.

?Dr. Veena S. Chakravarthi is the co-founder and adviser of SenseSemi Technologies, a developer of Internet of Things (IoT) solutions in healthcare, and is an expert in modern-day electronic systems on chip (SOC) solutions. She holds a doctoral degree from Bangalore University for her research work on generalized power optimization design methodologies for application-specific integrated circuits in VLSI. In her career spanning three decades, she has established herself as a leading architect of solutions in communications, optical, and wireless semiconductor domains specializing in high-performance and low power system on chips (SoCs). She started her career at ITI Limited, a premier public sector company, and later joined MindTree Consulting where she developed wireless IPs in Bluetooth and WLAN technologies. She has worked at Centillium India Ltd and Transwitch India Ltd, where she was involved in the development of Gigabit EPON chipsets. She has been a technical consultant for companies Ikanos Communications, Periera Ventures, and recently, Asarva Chips & Technologies. Dr. Chakravarthi is the inventor on six pending and two granted patents in the area of IoMT and is the author of the books A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide (Springer, 2019) and Internet of Things and M2M Communication Technologies (Springer, 2021).  She has authored numerous papers in the field of VLSI and healthcare and has held Chair and Vice-Chair positions with the IEEE Nanotechnology Council (NTC), Bangalore Section. She is a senior IEEE member.

Dr. Shivananda R. Koteshwar has more than 25 years of experience in the semiconductor industry. He is currently the Design Group Digital Implementation Site Leader and Head of R&D with Synopsys India. He is a founding trustee of the Belakoo Trust, which focuses on rural education, skills development, and experiential learning, and is a trustee of Aurinko Trust, whose flagship product is The Aurinko Academy, a progressive K12 school with career-focused programs in all streams. His startup portfolio includes Your Philanthropy Story, Ultraadox, FabSkool, and KreedaLoka. Dr. Koteshwar received a doctorate in Education Management from the Indian Institute of Management Bangalore (IIMB), a Postgraduate Diploma in Innovation and Design Thinking from the Emeritus Institute of Management, a Master's in Electrical Engineering from the OGI School of Science and Engineering, and BTech in Electronics and Communication Engineering from Mysore University. He is extremely active in mentoring start-ups catering to EdTech and the learning space and has served as a visiting faculty member in engineering design and management for several leading colleges and universities in India. He is currently an adjunct professor at Dayananda Sagar University and ISBR Business School.  

Produkt-Details

• Erscheint lt. Verlag: 6.6.2022
• Zusatzinfo: XXIV, 155 p. 106 illus., 80 illus. in color.
• Sprache: englisch
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Analog Chip Design • Clock Tree synthesis • Fabless Manufacturing • microchips • SOC design • Standard cell library • System on chip • Tape Out • Unified Power Format (UPF) Flow • VLSI Floor Plan and Placement • VLSI physical design
• ISBN-10: 3-030-98112-6 / 3030981126
• ISBN-13: 978-3-030-98112-9 / 9783030981129