Robust SRAM Designs and Analysis

Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan (Autoren)

Buch | Softcover

168 Seiten

2014
Springer-Verlag New York Inc.
978-1-4939-0244-6 (ISBN)

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This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.

Provides a complete and concise introduction to SRAM bitcell design and analysis;
Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;
Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;
Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

Introduction to SRAM.- Design Metrics of SRAM Bitcell.- Single-ended SRAM Bitcell Design.- 2-Port SRAM Bitcell Design.- SRAM Bitcell Design Using Unidirectional Devices.- NBTI and its Effect on SRAM.

Erscheint lt. Verlag	8.8.2014
Zusatzinfo	XII, 168 p.
Verlagsort	New York
Sprache	englisch
Maße	155 x 235 mm
Themenwelt	Technik ► Elektrotechnik / Energietechnik
Schlagworte	Emerging Memory • Power-aware circuit design • Power-aware memory design • SRAM bitcell • Static Random Access Memory • System-on-Chip • Tunnel FET • Variation-tolerant memory design
ISBN-10	1-4939-0244-X / 149390244X
ISBN-13	978-1-4939-0244-6 / 9781493902446
Zustand	Neuware