Designer's Guide to VHDL (eBook)

Peter J. Ashenden (Autor)

eBook Download: EPUB

2010 | 3. Auflage
936 Seiten
Elsevier Science (Verlag)
978-0-08-056885-0 (ISBN)

Infos

VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.

* First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard...helps readers get up to speed quickly with new features of the new standard.
* Presents a structured guide to the modeling facilities offered by VHDL...shows how VHDL functions to help design digital systems.
* Includes extensive case studies and source code used to develop testbenches and case study examples..helps readers gain maximum facility with VHDL for design of digital systems.

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VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. The Designer's Guide to VHDL has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008. - First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard- Helps readers get up to speed quickly with new features of the new standard- Presents a structured guide to the modeling facilities offered by VHDL- Shows how VHDL functions to help design digital systems- Includes extensive case studies and source code used to develop testbenches and case study examples- Helps readers gain maximum facility with VHDL for design of digital systems

Inhalt

Front Cover 1
The Designer’s Guide to VHDL 4
Copyright Page 5
Contents 8
Preface 18
Chapter 1. Fundamental Concepts 24
1.1 Modeling Digital Systems 24
1.2 Domains and Levels of Modeling 26
1.3 Modeling Languages 30
1.4 VHDL Modeling Concepts 30
1.5 Learning a New Language: Lexical Elements and Syntax 39
Exercises 52
Chapter 2. Scalar Data Types and Operations 54
2.1 Constants and Variables 54
2.2 Scalar Types 57
2.3 Type Classification 74
2.4 Attributes of Scalar Types 77
2.5 Expressions and Predefined Operations 80
Exercises 85
Chapter 3. Sequential Statements 88
3.1 If Statements 88
3.2 Case Statements 92
3.3 Null Statements 98
3.4 Loop Statements 99
3.5 Assertion and Report Statements 110
Exercises 116
Chapter 4. Composite Data Types and Operations 118
4.1 Arrays 118
4.2 Unconstrained Array Types 128
4.3 Array Operations and Referencing 137
4.4 Records 151
Exercises 157
Chapter 5. Basic Modeling Constructs 160
5.1 Entity Declarations and Architecture Bodies 160
5.2 Behavioral Descriptions 166
5.3 Structural Descriptions 199
5.4 Design Processing 209
Exercises 220
Chapter 6. Subprograms 230
6.1 Procedures 230
6.2 Procedure Parameters 236
6.3 Concurrent Procedure Call Statements 248
6.4 Functions 250
6.5 Overloading 256
6.6 Visibility of Declarations 259
Exercises 263
Chapter 7. Packages and Use Clauses 268
7.1 Package Declarations 268
7.2 Package Bodies 275
7.3 Use Clauses 280
Exercises 287
Chapter 8. Resolved Signals 290
8.1 Basic Resolved Signals 290
8.2 Resolved Signals, Ports, and Parameters 303
Exercises 310
Chapter 9. Predefined and Standard Packages 316
9.1 The Predefined Packages standard and env 316
9.2 IEEE Standard Packages 319
Exercises 358
Chapter 10 Case Study: A Pipelined Multiplier Accumulator 360
10.1 Algorithm Outline 360
10.2 A Behavioral Model 363
10.3 A Register-Transfer-Level Model 369
Exercises 376
Chapter 11. Aliases 378
11.1 Aliases for Data Objects 378
11.2 Aliases for Non-Data Items 383
Exercises 386
Chapter 12. Generics 388
12.1 Generic Constants 388
12.2 Generic Types 395
12.3 Generic Lists in Packages 399
12.4 Generic Lists in Subprograms 412
12.5 Generic Subprograms 417
12.6 Generic Packages 430
Exercises 437
Chapter 13. Components and Configurations 440
13.1 Components 440
13.2 Configuring Component Instances 445
13.3 Configuration Specifications 460
Exercises 467
Chapter 14. Generate Statements 472
14.1 Generating Iterative Structures 472
14.2 Conditionally Generating Structures 478
14.3 Configuration of Generate Statements 488
Exercises 496
Chapter 15. Access Types 502
15.1 Access Types 502
15.2 Linked Data Structures 509
15.3 An Ordered-Dictionary ADT Using Access Types 514
Exercises 518
Chapter 16. Files and Input/Output 522
16.1 Files 522
16.2 The Package Textio 537
Exercises 553
Chapter 17. Case Study: A Package for Memories 558
17.1 The Memories Package 558
17.2 Using the Memories Package 569
Exercises 581
Chapter 18. Test Bench and Verification Features 582
18.1 External Names 582
18.2 Force and Release Assignments 593
18.3 Embedded PSL in VHDL 598
Exercises 605
Chapter 19. Shared Variables and Protected Types 608
19.1 Shared Variables and Mutual Exclusion 608
19.2 Uninstantiated Methods in Protected Types 620
Exercises 624
Chapter 20. Attributes and Groups 626
20.1 Predefined Attributes 626
20.2 User-Defined Attributes 639
20.3 Groups 651
Exercises 653
Chapter 21. Design for Synthesis 656
21.1 Synthesizable Subsets 656
21.2 Use of Data Types 657
21.3 Interpretation of Standard Logic Values 660
21.4 Modeling Combinational Logic 661
21.5 Modeling Sequential Logic 664
21.6 Modeling Memories 677
21.7 Synthesis Attributes 681
21.8 Metacomments 689
Exercises 690
Chapter 22. Case Study: System Design Using the Gumnut Core 692
22.1 Overview of the Gumnut 692
22.2 A Behavioral Model 704
22.3 A Register-Transfer-Level Model 727
22.4 A Digital Alarm Clock 744
Exercises 754
Chapter 23. Miscellaneous Topics 756
23.1 Guards and Blocks 756
23.2 IP Encryption 773
23.3 VHDL Procedural Interface (VHPI) 793
23.4 Postponed Processes 799
23.5 Conversion Functions in Association Lists 802
23.6 Linkage Ports 808
Exercises 809
Appendix A: Standard Packages 816
A.1 The Predefined Package standard 816
A.2 The Predefined Package env 820
A.3 The Predefined Package textio 820
A.4 Standard VHDL Mathematical Packages 822
A.5 The std_logic_1164 Multivalue Logic System Package 825
A.6 Standard Integer Numeric Packages 829
A.7 Standard Fixed-Point Packages 839
A.8 Standard Floating-Point Packages 852
Appendix B: VHDL Syntax 864
B.1 Design File 866
B.2 Library Unit Declarations 866
B.3 Declarations and Specifications 868
B.4 Type Definitions 871
B.5 Concurrent Statements 873
B.6 Sequential Statements 875
B.7 Interfaces and Associations 878
B.8 Expressions and Names 879
Appendix C: Answers to Exercises 882
References 912
Index 914

Produkt-Details

• Erscheint lt. Verlag: 7.10.2010
• Sprache: englisch
• Themenwelt: Sachbuch/Ratgeber
• Themenwelt: Mathematik / Informatik ► Informatik ► Programmiersprachen / -werkzeuge
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• ISBN-10: 0-08-056885-8 / 0080568858
• ISBN-13: 978-0-08-056885-0 / 9780080568850