Analog Circuit Design (eBook)

Robust Design, Sigma Delta Converters, RFID

Herman Casier, Michiel Steyaert, Arthur H.M. van Roermund (Herausgeber)

eBook Download: PDF

2011 | 2011
XIV, 367 Seiten
Springer Netherland (Verlag)
978-94-007-0391-9 (ISBN)

Infos

 Analog Circuit Design contains the contribution of 18 tutorials of the 19th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of:

• Robust Design,
  chaired by Herman Casier, Consultant
• Sigma Delta Converters,
  chaired by Prof. Michiel Steyaert, Catholic University Leuven
• RFID,
  chaired by Prof. Arthur van Roermund, Eindhoven University of Technology

Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design course.

Inhalt

Preface 5
Contents 8
Contributors 10
Part I Robust Design 14
Modeling and Design for Reliability of Analog Integrated Circuits in Nanometer CMOS Technologies 16
1 Introduction 16
2 Variability- and Reliability-Induced Analog Circuit Performance Degradation 17
2.1 Variability and Mismatch 17
2.2 Time-Dependent Degradation 18
2.2.1 Time-Dependent Dielectric Breakdown 19
2.2.2 Hot-Carrier Injection 19
2.2.3 Negative Bias Temperature Instability 19
3 Reliability Analysis of Analog Integrated Circuits 20
3.1 Illustrative Circuit Example 22
4 Circuit Techniques for Variability and Degradation Resilience 24
4.1 Solutions to Processing Variability 24
4.2 Solutions to Time-Dependent Degradation 25
5 Conclusions 28
References 28
Modeling and Simulation of Statistical Variability in Nanometer CMOS Technologies 30
2 Sources of Statistical Variability 31
3 Statistical Variability in Advanced CMOS Devices 32
4 Statistical Compact Model Strategy 39
5 Impact of Statistical Variability on SRAM 42
6 Conclusions 44
References 45
Advanced Physical Design in Nanoscale Analog CMOS 47
2 Pre-Layout Simulation 48
3 Post-Layout Simulation 49
4 Process Variability 50
5 Mitigating Local Mismatch Errors 51
5.1 Quantum-Effect Mismatch Errors 51
5.2 Stress-Induced Mismatch Factors 52
5.3 High-Frequency Device Matching 52
5.4 Strategy for Matching as Devices are Downscaled 52
6 HF Analog Device Physical Design 54
6.1 Restricting the Number of Gate Fingers (F) 54
6.2 Device Optimum Current Density Ids/(W/L) Under Scaling 55
6.3 EM Limitations Forcing Use of Multiple Metal Layers 55
6.4 Achieving Good Pattern Fidelity in Device Design 56
7 Mitigating Long-Distance Mismatch Errors in Precision Circuits 59
8 Interconnect Physical Design 60
8.1 Clock and Shielded Analog Signal Distribution Physical Design 60
8.2 Dense Metal Interconnect Physical Design 61
9 Summary and Conclusions 62
References 62
Robust Design for High Temperature and High Voltage Applications 64
2 Nanoelectronics Semiconductor Technologies for Power Devices for EVs and HEVs Applications 68
3 Robustness, Reliability, Dependability 68
3.1 Safe Operating Area 73
4 Simulation 74
4.1 Electro-Thermal Simulation 74
4.2 Reliability Prediction by Ageing Simulation 74
5 Packaging and Interconnects 75
5.1 Metal Carbon Nanotube Composites for High Temperature Applications 76
5.2 Thermal Management 76
6 Conclusions 77
References 78
Radiation Effects and Hardening by Design in CMOS Technologies 79
2 Radiation Effects in Modern CMOS Technologies 80
2.1 TID Effects 80
2.2 Single Event Effects (SEEs) 84
3 The Hardness By Design (HBD) Approach 86
3.1 HBD for TID Effects 86
3.2 HBD for Single Event Effects 91
4 Conclusion 95
References 96
EMC Robust Design for Smart Power High Side Switches 98
2 High Side Switches in Smart Power Technology 99
3 DPI Test for High Side Switches—Measurement Method 100
3.3 Operation Modes of the IC Under Test 102
4 DPI Test for High Side Switches—Simulation Approach 102
5 DPI Robustness in Off State—Problem Description 104
6 Design Methodology—Pin Impedance Design 105
7 Measurement Results 110
8 Conclusion 112
References 113
Part II Sigma Delta Converters 114
Noise-Coupled Delta-Sigma ADCS 116
2 Noise-coupled .S ADCs 117
2.1 Quantization noise self coupling (QNSC) 117
2.2 Quantization noise cross-coupling and time-interleaving (NCTI) 123
3 SC circuit implementation 129
4 Experimental Results 133
4.1 QNSC prototype .S ADC 133
4.2 NCTI prototype .S ADCs 137
5 Conclusions 334
References 334
Very Low OSR Sigma-Delta Converters 143
2 Background Information 144
2.1 Delta-Sigma Modulators 144
2.2 Incremental Data Converters 146
3 High-Order MASH S. Modulator 148
3.1 Comparison with a Nyquist-Rate A/D Converter 149
3.2 Single-Stage vs. Cascaded S. 150
3.3 Sample Architecture 151
3.4 Power Efficiency 153
4 Incremental Data Converters 156
4.1 Comparison of Incremental and S. Converters 156
4.2 Pipeline Equivalency 158
4.3 Removing the Input S/H 160
4.4 Sample Architecture 162
5 Conclusions 334
References 368
Comparator-Based Switched-Capacitor Delta-Sigma A/D Converters 165
2 Switched-Capacitor Integrator 166
3 CBSC: Comparator 170
3.1 Comparator Delay 170
3.2 Comparator Offset 171
3.3 Comparator Noise 172
3.4 Zero-Crossing Based Implementation 173
4 CBSC: Current Source 174
4.1 Current Source Sizing 174
4.2 Current Source Output Resistance 174
4.3 Current Source Noise 174
4.4 High Output Swing Implementation 175
5 CBSC Noise-Shaping Filter 176
6 A CBSC Delta-Sigma A/D Converter in 90 nm CMOS 178
7 Conclusions 183
References 368
VCO-Based Wideband Continuous-Time Sigma-Delta Analog-to-Digital Converters 185
2 Background on VCO-Based Quantization 186
3 A First Pass at Utilizing VCO-Based Quantization Within Continuous-Time Sigma-Delta ADC Structures 191
4 Overcoming the Issue of Nonlinearity in the VCO-Based Quantizer 193
5 Striving for 80 dB SNDR with 20 MHz Bandwidth 195
6 Circuit Details of a 4th Order, Continuous-Time Sigma-Delta ADC Prototype in 0.13 µ CMOS 199
6.1 VCO-Based Quantizer 199
6.2 Opamp Design 201
6.3 DAC Designs 201
6.4 DEM Design 203
6.5 Overall Implementation in 0.13 µ CMOS 204
7 Measured Results of the Prototype 204
8 Conclusions 207
References 207
Wideband Continuous-Time Multi-Bit Delta-Sigma ADCs 210
2 A 20 MHz 68 dB Dynamic Range .S ADC Based on Time-Domain Quantizer and Feedback Element 211
2.1 Multi-Bit Time-Based ADC Architecture [12, 13] 212
2.2 Lowpass Filter Design 212
2.3 Time-Domain Quantizer 214
2.4 Spectrum of the PWM Signal DAC 215
2.5 Design Considerations 216
2.6 Experimental Results 219
3 A 5th-Order Continuous-Time Lowpass .S Modulator [18] 220
3.1 Multi-Bit ADC Architecture 220
3.2 Design Considerations 220
3.2.1 Jitter Sensitivity 220
3.2.2 Static Device Mismatch 222
3.3 Filter and Summing Amplifier 224
3.4 Three-Bit Two-Step Quantizer 225
3.5 Level-to-PWM Converter 227
3.6 Clock Generator 229
3.7 Simulated and Experimental Results 230
4 Conclusion 232
References 232
OVERSAMPLED DACs 234
2 Specification Analysis 236
2.1 In-band Dynamic Range (DR) 236
2.2 Low Power Consumption 238
2.3 Single-Ended Output 238
2.4 Fully Integrability 238
2.5 Performance Robustness 238
2.6 Accurate In-band and Out-of-band Frequency Response 240
2.7 Out-of-band SNRout 240
2.8 Output Power Stage 241
3 Audio-DAC Design Trade-off 241
4 Digital-to-Analog Interface 242
4.1 Single-Bit vs. Multibit 242
4.2 Switched-Capacitor D/A Interface 243
4.3 Switched-Current 245
5 Advanced Oversampled DACs 249
5.1 Increasing the Quantizer Output Number of Bit 249
5.2 Embedding Power Stage in the Analog Filter 249
5.3 Improving PSRR 252
5.4 Cascaded S.M 252
5.5 Improved S.M for Idle-Tone Reduction 255
5.6 Hybrid DAC 256
6 High-Speed Oversampled DAC 261
References 261
Part III RFID 263
RFID, a Technology Ready for Industry Deployment 265
1 RFID History 265
2 RFID Market Landscape 267
3 RFID Standards 268
3.1 The Core Architecture 268
3.2 The Formation of ISO/IEC JTC1 SC31 WG4 270
3.3 RFID Standards and Applications Before the Epoch 270
3.4 Bar Code Applications and Application Standards Before the Epoch 271
3.5 Early RFID Standardisation Activities 272
3.6 ISO/IEC JTC1 SC31 WG4 273
4 The BRIDGE Project 273
4.1 Project Overview 273
4.2 BRIDGE Hardware Developments 276
5 Privacy Concerns 279
6 Regulations 280
7 Conclusion 281
References 281
The World’s Smallest RFID Chip Technology 283
2 Chip Design Concept 284
2.1 Chip Architecture 284
2.2 Mechanical Endurance 285
2.3 High-Reliability Electron Beam Written ID Memory 285
3 Antenna Design Concept 288
3.1 Embedded Antenna 288
3.2 External Antenna on Double-Surface Electrode Chip 288
4 Silicon on Insulator (SOI) Ultra-thin RFID Chip 291
5 Conclusions 334
References 334
RF and Low Power Analog Design for RFID 294
2 Rectifiers for UHF and HF RFID Tags 295
2.1 General Rectifier Topologies 296
2.2 UHF Rectifier Design 297
2.3 HF Rectifier Design 303
3 Power Management Design for RFID 304
3.1 RF Limiter Design 305
3.2 DC Limiter Design 307
3.3 Regulator Design 308
4 RFID Data Receiver Design and Additional Support Circuits 310
4.1 Data Receiver Design 310
4.2 Data Slicer Design 312
4.3 Additional RFID Circuits 314
5 Flexible Organic Semiconductor RFID Tags 314
6 Conclusions 315
References 316
A Dual Frequency Band Comprehensive RFID TAG 317
1 Introduction 317
2 HF and UHF Power Generation with One Antenna Port 321
2.1 Power Generator Architecture 323
2.2 Multi Frequency Rectifier 324
2.3 DC/DC Down Converter 326
2.4 DC/DC Up Converter 327
3 Local Oscillator 328
4 Units for Contactless Communication 330
4.1 HF RxD Unit 330
4.2 UHF RxD Unit 331
4.3 Shunt, TxD—Load Modulator and Backscatter Unit 332
5 Conclusions 334
References 334
Printed Electronics—First Circuits, Products, and Roadmap 336
1 Introduction 336
2 Printed Electronics 337
3 First Printed Circuits 339
3.1 Printed Ring Oscillator 340
3.2 Printed 4-Bit Manchester Chip 341
4 First Products and Roadmap of Printed Electronics 342
4.1 Roadmap for Organic Electronics 342
4.2 Roadmap for Printed RFID 344
4.3 First RFID Products 346
5 Summary 347
References 347
Towards EPC-Compatible Organic RFID Tags 349
1 Introduction 349
2 Organic RFID Tags 350
2.1 Technology 350
2.2 The RFID Measurement Setup 352
2.3 Organic Transponder Chip 353
2.4 Organic Rectifier 354
2.5 Organic RFID Tag Using DC Load Modulation 356
3 Methods to Increase Robustness of Digital Circuits 358
3.1 Organic RFID Transponder Chip with Dual-Gate Architecture 361
4 Vision for Commercialization 362
5 A 50 kHz RFID Transponder Chip 363
6 Conclusions 368
References 368

Produkt-Details

• Erscheint lt. Verlag: 1.2.2011
• Zusatzinfo: XIV, 367 p.
• Verlagsort: Dordrecht
• Sprache: englisch
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Analog Circuit Design • RF • Robust Design • wireless communications
• ISBN-10: 94-007-0391-0 / 9400703910
• ISBN-13: 978-94-007-0391-9 / 9789400703919