A Guide to Modern ASIC Design
Cambridge University Press (Verlag)
978-0-521-19672-7 (ISBN)
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From register transfer level (RTL) to logic synthesis, this practical guide describes the complete modern ASIC front-end design flow. Written in a systematic style, and integrating ASIC design theory and methodology with real design challenges, this book enables you to follow the design process and learn the key considerations for successful implementation of a silicon chip. Starting with writing synthesizable RTL and recommended coding styles, you'll then learn design partitioning and logic synthesis strategies before moving on to more advanced topics such as Synopsys Design Compiler Topographical (DCT) synthesis, low power design based on Unified Power Format (UPF) and Design for Test (DFT). Topics are made easy to follow with over 400 illustrations, whilst 200 practical examples and real-life design scenarios help you to avoid costly design pitfalls. Whether you're a student studying VLSI or a practising engineer in the IC design industry, this practical guide will get you up to speed on ASIC design.
Victor X. Q. Yu is Application Consultant Lead at Synopsys International Inc., where he has worked since 2000. Prior to joining Synopsys, he held positions at various companies, including Telecom Technology Center, Mentor Graphics and Synthesis System Design Limited. He also spent time as an Assistant Lecturer at the Zhejiang University in Hong Zhou, China, where he taught courses in digital electronics and CAD. Albert T. L. Lee is a Ph.D. candidate at the Hong Kong University of Science and Technology (HKUST). After receiving his MS degree at the University of Michigan, Ann Arbor, he spent four years with the Intel Corporation, Hillsboro, Oregon, where he won several Intel design awards, including the 1999 Q4 D1 Divisional Recognition Award, LTD Microprocessor Design Group Awards for Coppermine in July 1999 and COP-X in September 1999. Philip C. H. Chan is a Professor in the Department of Electronics and Computer Engineering at the HKUST, where he first joined as a founding faculty member in 1991. Prior to joining HKUST, he spent 10 years at the Intel Corporation, Santa Clara, California, where he worked on technology development, design technology (CAD), packaging technology development, multichip module technology and product development. He is a Fellow of the IEEE and holds 10 international patents.
1. Introduction; 2. RTL modeling for combinational logic; 3. RTL modeling for sequential logic; 4. RTL coding guidelines; 5. Synthesis and technology library; 6. Design hierarchy and partitioning for synthesis; 7. Design goals and constraints; 8. Design optimization and compile strategies; 9. Topographical synthesis; 10. Low power design and analysis; 11. Design for Test.
| Erscheint lt. Verlag | 1.7.2010 |
|---|---|
| Zusatzinfo | Worked examples or Exercises; 12 Tables, black and white; 400 Line drawings, black and white |
| Verlagsort | Cambridge |
| Sprache | englisch |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 0-521-19672-8 / 0521196728 |
| ISBN-13 | 978-0-521-19672-7 / 9780521196727 |
| Zustand | Neuware |
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