Nicht aus der Schweiz? Besuchen Sie lehmanns.de
Für diesen Artikel ist leider kein Bild verfügbar.

Digital System Verification

A Combined Formal Methods and Simulation Framework
Buch | Softcover
93 Seiten
2010
Morgan & Claypool Publishers (Verlag)
978-1-60845-178-4 (ISBN)
CHF 67,95 inkl. MwSt
  • Lieferbar
  • Versandkostenfrei
  • Auch auf Rechnung
  • Artikel merken
Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative.

This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation.

Introduction
Formal Methods Background
Simulation Approaches
Integrated Design Validation System
Conclusion and Summary

Reihe/Serie Synthesis Lectures on Digital Circuits and Systems
Verlagsort San Rafael
Sprache englisch
Maße 187 x 235 mm
Themenwelt Technik Elektrotechnik / Energietechnik
ISBN-10 1-60845-178-X / 160845178X
ISBN-13 978-1-60845-178-4 / 9781608451784
Zustand Neuware
Haben Sie eine Frage zum Produkt?
Mehr entdecken
aus dem Bereich
DIN-Normen und Technische Regeln für die Elektroinstallation

von DIN; ZVEH; Burkhard Schulze

Buch | Softcover (2023)
Beuth (Verlag)
CHF 119,95

von Jan Luiken ter Haseborg; Christian Schuster; Manfred Kasper

Buch | Hardcover (2023)
Carl Hanser (Verlag)
CHF 48,95