ASIC and FPGA Verification (eBook)

A Guide to Component Modeling

Richard Munden (Autor)

eBook Download: PDF

2004 | 1. Auflage
336 Seiten
Elsevier Science (Verlag)
978-0-08-047592-9 (ISBN)

Infos

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model off-the-shelf or IP digital components for use in FPGA and board-level design verification.

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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.*Provides numerous models and a clearly defined methodology for performing board-level simulation.*Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "e;off-the-shelf"e; or "e;IP"e; digital components for use in FPGA and board-level design verification.

Inhalt

Front cover 1
ABOUT THE AUTHOR 3
Title page 4
Copyright Page 6
Table of Contents 8
PREFACE 16
Historical Background 16
Verilog, VHDL, and the Origin of VITAL 17
The VITAL Specification 17
The Free Model Foundry 18
Structure of the Book 19
Intended Audience 20
Resources for Help and Information 20
Acknowledgments 21
PART I INTRODUCTION 22
CHAPTER 1 INTRODUCTION TO BOARD-LEVEL VERIFICATION 24
1.1 Why Models Are Needed 24
1.1.1 Prototyping 24
1.1.2 Simulation 25
1.2 Definition of a Model 26
1.2.1 Levels of Abstraction 27
1.2.2 Model Types 28
1.2.3 Technology-Independent Models 30
1.3 Design Methods and Models 31
1.4 How Models Fit in the FPGA/ASIC Design Flow 31
1.4.1 The Design/Verification Flow 32
1.5 Where to Get Models 34
1.6 Summary 35
CHAPTER 2 TOUR OF A SIMPLE MODEL 36
2.1 Formatting 36
2.2 Standard Interfaces 38
2.3 Model Delays 39
2.4 VITAL Additions 40
2.4.1 VITAL Delay Types 40
2.4.2 VITAL Attributes 41
2.4.3 VITAL Primitive Call 42
2.4.4 VITAL Processes 43
2.4.5 VitalPathDelays 45
2.5 Interconnect Delays 46
2.6 Finishing Touches 48
2.7 Summary 52
PART II RESOURCES AND STANDARDS 54
CHAPTER 3 VHDL PACKAGES FOR COMPONENT MODELS 56
3.1 STD_LOGIC_1164 56
3.1.1 Type Declarations 57
3.1.2 Functions 58
3.2 VITAL_Timing 58
3.2.1 Declarations 58
3.2.2 Procedures 59
3.3 VITAL_Primitives 60
3.3.1 Declarations 61
3.3.2 Functions and Procedures 61
3.4 VITAL_Memory 62
3.4.1 Memory Functionality 62
3.4.2 Memory Timing Specification 63
3.4.3 Memory Timing Checks 63
3.5 FMF Packages 63
3.5.1 FMF gen_utils and ecl_utils 64
3.5.2 FMF ff_package 65
3.5.3 FMF Conversions 66
3.6 Summary 66
CHAPTER 4 AN INTRODUCTION TO SDF 68
4.1 Overview of an SDF File 68
4.1.1 Header 69
4.1.2 Cell 71
4.1.3 Timing Specifications 71
4.2 SDF Capabilities 73
4.2.1 Circuit Delays 73
4.2.2 Timing Checks 76
4.3 Summary 79
CHAPTER 5 ANATOMY OF A VITAL MODEL 80
5.1 Level 0 Guidelines 80
5.1.1 Backannotation 81
5.1.2 Timing Generics 81
5.1.3 VitalDelayTypes 82
5.2 Level 1 Guidelines 84
5.2.1 Wire Delay Block 84
5.2.2 Negative Constraint Block 86
5.2.3 Processes 87
5.2.4 VITAL Primitives 91
5.2.5 Concurrent Procedure Section 91
5.3 Summary 91
CHAPTER 6 MODELING DELAYS 94
6.1 Delay Types and Glitches 94
6.1.1 Transport and Inertial Delays 94
6.1.2 Glitches 95
6.2 Distributed Delays 96
6.3 Pin-to-Pin Delays 96
6.4 Path Delay Procedures 97
6.5 Using VPDs 103
6.6 Generates and VPDs 104
6.7 Device Delays 104
6.8 Backannotating Path Delays 109
6.9 Interconnect Delays 110
6.10 Summary 111
CHAPTER 7 VITAL TABLES 112
7.1 Advantages of Truth and State Tables 112
7.2 Truth Tables 113
7.2.1 Truth Table Construction 113
7.2.2 VITAL Table Symbols 113
7.2.3 Truth Table Usage 114
7.3 State Tables 118
7.3.1 State Table Symbols 118
7.3.2 State Table Construction 118
7.3.3 State Table Usage 119
7.3.4 State Table Algorithm 120
7.4 Reducing Pessimism 121
7.5 Memory Tables 122
7.5.1 Memory Table Symbols 122
7.5.2 Memory Table Construction 123
7.5.3 Memory Table Usage 124
7.6 Summary 127
CHAPTER 8 TIMING CONSTRAINTS 128
8.1 The Purpose of Timing Constraint Checks 128
8.2 Using Timing Constraint Checks in VITAL Models 129
8.2.1 Setup/Hold Checks 129
8.2.2 Period/Pulsewidth Checks 133
8.2.3 Recovery/Removal Checks 135
8.2.4 Skew Checks 138
8.3 Violations 142
8.4 Summary 143
PART III MODELING BASICS 144
CHAPTER 9 MODELING COMPONENTS WITH REGISTERS 146
9.1 Anatomy of a Flip-Flop 146
9.1.1 The Entity 146
9.1.2 The Architecture 150
9.1.3 A VITAL Process 152
9.1.4 Functionality Section 154
9.1.5 Path Delay 155
9.1.6 The “B” Side 156
9.2 Anatomy of a Latch 158
9.2.1 The Entity 159
9.2.2 The Architecture 161
9.3 Summary 167
CHAPTER 10 CONDITIONAL DELAYS AND TIMING CONSTRAINTS 168
10.1 Conditional Delays in VITAL 168
10.2 Conditional Delays in SDF 170
10.3 Conditional Delay Alternatives 171
10.4 Mapping SDF to VITAL 173
10.5 Conditional Timing Checks in VITAL 174
10.6 Summary 177
CHAPTER 11 NEGATIVE TIMING CONSTRAINTS 178
11.1 How Negative Constraints Work 178
11.2 Modeling Negative Constraints 179
11.3 How Simulators Handle Negative Constraints 197
11.4 Ramifications 198
11.5 Summary 199
CHAPTER 12 TIMING FILES AND BACKANNOTATION 200
12.1 Anatomy of a Timing File 200
12.1.1 Header 200
12.1.2 Body 202
12.1.3 FMFTIME 202
12.2 Separate Timing Specifications 203
12.3 Importing Timing Values 204
12.4 Custom Timing Sections 204
12.5 Generating Timing Files 205
12.6 Generating SDF Files 205
12.7 Backannotation and Hierarchy 206
12.8 Summary 208
PART IV ADVANCED MODELING 210
CHAPTER 13 ADDING TIMING TO YOUR RTL CODE 212
13.1 Using VITAL to Simulate Your RTL 212
13.2 The Basic Wrapper 213
13.3 A Wrapper for Verilog RTL 227
13.4 Modeling Delays in Designs with Internal Clocks 227
13.5 Caveats 228
13.6 Summary 229
CHAPTER 14 MODELING MEMORIES 230
14.1 Memory Arrays 230
14.1.1 The Shelor Method 231
14.1.2 The VITAL_Memory Package 232
14.2 Modeling Memory Functionality 232
14.2.1 Using the Behavioral (Shelor) Method 232
14.2.2 Using the VITAL2000 Method 244
14.3 VITAL_Memory Path Delays 252
14.4 VITAL_Memory Timing Constraints 253
14.5 Preloading Memories 256
14.5.1 Behavioral Memory Preload 256
14.5.2 VITAL_Memory Preload 258
14.6 Modeling Other Memory Types 259
14.6.1 Synchronous Static RAM 259
14.6.2 DRAM 262
14.6.3 SDRAM 265
14.7 Summary 270
CHAPTER 15 CONSIDERATIONS FOR COMPONENT MODELING 272
15.1 Component Models and Netlisters 272
15.2 File Contents 274
15.3 Generics Passed from the Schematic 274
15.3.1 Timing Generics 274
15.3.2 Control Generics 274
15.4 Integrating Models into a Schematic Capture System 275
15.4.1 Library Structure 275
15.4.2 Technology Independence 276
15.4.3 Directories 276
15.4.4 Map Files 277
15.5 Using Models in the Design Process 277
15.5.1 VHDL Libraries 278
15.5.2 Schematic Entry 278
15.5.3 Netlisting the Design 279
15.5.4 VHDL Compilation 280
15.5.5 SDF Generation 280
15.5.6 Simulation 282
15.5.7 Layout 282
15.5.8 Signal Analysis 283
15.5.9 Timing Backannotation 283
15.5.10 Timing Analysis 283
15.6 Special Considerations 283
15.6.1 Schematic Considerations 283
15.6.2 Model Considerations 284
15.7 Summary 287
CHAPTER 16 MODELING COMPONENT-CENTRIC FEATURES 290
16.1 Differential Inputs 290
16.2 Bus Hold 300
16.3 PLLs and DLLs 303
16.4 Assertions 305
16.5 Modifying Behavior with the TimingModel Generic 306
16.6 State Machines 306
16.7 Mixed Signal Devices 309
16.8 Summary 315
CHAPTER 17 TESTBENCHES FOR COMPONENT MODELS 316
17.1 About Testbenches 316
17.1.1 Tools 316
17.2 Testbench Styles 317
17.2.1 The Empty Testbench 317
17.2.2 The Linear Testbench 317
17.2.3 The Transactor Testbench 317
17.3 Using Assertions 318
17.4 Using Transactors 319
17.5 Testing Memory Models 322
17.6 Summary 329
Index 330

Produkt-Details

• Erscheint lt. Verlag: 23.10.2004
• Sprache: englisch
• Themenwelt: Sachbuch/Ratgeber
• Themenwelt: Mathematik / Informatik ► Informatik ► Datenbanken
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• ISBN-10: 0-08-047592-2 / 0080475922
• ISBN-13: 978-0-08-047592-9 / 9780080475929