Digital Design and Computer Architecture (eBook)

David Harris, Sarah Harris (Autoren)

eBook Download: EPUB

2010 | 1. Auflage
592 Seiten
Elsevier Science (Verlag)
9780080547060 (ISBN)

Infos

Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works--even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design.
· Unique presentation of digital logic design from the perspective of computer architecture using a real instruction set, MIPS.
· Side-by-side examples of the two most prominent Hardware Design Languages--VHDL and Verilog--illustrate and compare the ways the each can be used in the design of digital systems.
· Worked examples conclude each section to enhance the reader's understanding and retention of the material.
· Companion Web site includes links to CAD tools for FPGA design from Xilinx, lecture slides, laboratory projects, and solutions to exercises.

David Money Harris is an associate professor of engineering at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Evans & Sutherland, and other design companies.
David's passions include teaching, building chips, and exploring the outdoors. When he is not at work, he can usually be found hiking, mountaineering, or rock climbing. He particularly enjoys hiking with his son, Abraham, who was born at the start of this book project. David holds about a dozen patents and is the author of three other textbooks on chip design, as well as two guidebooks to the Southern California mountains.

Inhalt

Front cover 1
In Praise of Digital Design and Computer Architecture 2
About the Authors 5
Title page 6
Copyright page 7
Table of contents 10
Preface 18
FEATURES 19
ONLINE SUPPLEMENTS 20
HOW TO USE THE SOFTWARE TOOLS IN A COURSE 20
Xilinx ISE WebPACK 20
Synplify Pro 21
PCSPIM 21
LABS 21
BUGS 22
ACKNOWLEDGMENTS 22
Chapter 1 From Zero to One 26
1.1 THE GAME PLAN 26
1.2 THE ART OF MANAGING COMPLEXITY 27
1.2.1 Abstraction 27
1.2.2 Discipline 28
1.2.3 The Three -Y’s 29
1.3 THE DIGITAL ABSTRACTION 30
1.4 NUMBER SYSTEMS 32
1.4.1 Decimal Numbers 32
1.4.2 Binary Numbers 32
1.4.3 Hexadecimal Numbers 34
1.4.4 Bytes, Nibbles, and All That Jazz 36
1.4.5 Binary Addition 37
1.4.6 Signed Binary Numbers 38
1.5 LOGIC GATES 42
1.5.1 NOT Gate 43
1.5.2 Buffer 43
1.5.3 AND Gate 43
1.5.4 OR Gate 44
1.5.5 Other Two-Input Gates 44
1.5.6 Multiple-Input Gates 44
1.6 BENEATH THE DIGITAL ABSTRACTION 45
1.6.1 Supply Voltage 45
1.6.2 Logic Levels 45
1.6.3 Noise Margins 46
1.6.4 DC Transfer Characteristics 46
1.6.5 The Static Discipline 47
1.7 CMOS TRANSISTORS 49
1.7.1 Semiconductors 50
1.7.2 Diodes 50
1.7.3 Capacitors 51
1.7.4 nMOS and pMOS Transistors 51
1.7.5 CMOS NOT Gate 54
1.7.6 Other CMOS Logic Gates 54
1.7.7 Transmission Gates 56
1.7.8 Pseudo-nMOS Logic 56
1.8 POWER CONSUMPTION 57
1.9 SUMMARY AND A LOOK AHEAD 58
Exercises 60
Interview Questions 71
Chapter 2 Combinational Logic Design 74
2.1 INTRODUCTION 74
2.2 BOOLEAN EQUATIONS 77
2.2.1 Terminology 77
2.2.2 Sum-of-Products Form 77
2.2.3 Product-of-Sums Form 79
2.3 BOOLEAN ALGEBRA 79
2.3.1 Axioms 80
2.3.2 Theorems of One Variable 80
2.3.3 Theorems of Several Variables 81
2.3.4 The Truth Behind It All 83
2.3.5 Simplifying Equations 84
2.4 FROM LOGIC TO GATES 85
2.5 MULTILEVEL COMBINATIONAL LOGIC 88
2.5.1 Hardware Reduction 89
2.5.2 Bubble Pushing 90
2.6 X’S AND Z’S, OH MY 92
2.6.1 Illegal Value: X 92
2.6.2 Floating Value: Z 93
2.7 KARNAUGH MAPS 94
2.7.1 Circular Thinking 95
2.7.2 Logic Minimization with K-Maps 96
2.7.3 Don’t Cares 100
2.7.4 The Big Picture 101
2.8 COMBINATIONAL BUILDING BLOCKS 102
2.8.1 Multiplexers 102
2.8.2 Decoders 105
2.9 TIMING 107
2.9.1 Propagation and Contamination Delay 107
2.9.2 Glitches 111
2.10 SUMMARY 114
Exercises 116
Interview Questions 123
Chapter 3 Sequential Logic Design 126
3.1 INTRODUCTION 126
3.2 LATCHES AND FLIP-FLOPS 126
3.2.1 SR Latch 128
3.2.2 D Latch 130
3.2.3 D Flip-Flop 131
3.2.4 Register 131
3.2.5 Enabled Flip-Flop 132
3.2.6 Resettable Flip-Flop 133
3.2.7 Transistor-Level Latch and Flip-Flop Designs 133
3.2.8 Putting It All Together 135
3.3 SYNCHRONOUS LOGIC DESIGN 136
3.3.1 Some Problematic Circuits 136
3.3.2 Synchronous Sequential Circuits 137
3.3.3 Synchronous and Asynchronous Circuits 139
3.4 FINITE STATE MACHINES 140
3.4.1 FSM Design Example 140
3.4.2 State Encodings 146
3.4.3 Moore and Mealy Machines 149
3.4.4 Factoring State Machines 152
3.4.5 FSM Review 155
3.5 TIMING OF SEQUENTIAL LOGIC 156
3.5.1 The Dynamic Discipline 157
3.5.2 System Timing 158
3.5.3 Clock Skew 163
3.5.4 Metastability 166
3.5.5 Synchronizers 167
3.5.6 Derivation of Resolution Time 169
3.6 PARALLELISM 172
3.7 SUMMARY 176
Exercises 178
Untitled 188
Chapter 4 Hardware Description Languages 190
4.1 INTRODUCTION 190
4.1.1 Modules 190
4.1.2 Language Origins 191
4.1.3 Simulation and Synthesis 192
4.2 COMBINATIONAL LOGIC 194
4.2.1 Bitwise Operators 194
4.2.3 Reduction Operators 197
4.2.2 Comments and White Space 197
4.2.4 Conditional Assignment 198
4.2.5 Internal Variables 199
4.2.6 Precedence 201
4.2.7 Numbers 202
4.2.8 Z’s and X’s 202
4.2.9 Bit Swizzling 205
4.2.10 Delays 205
4.2.11 VHDL Libraries and Types 206
4.3 STRUCTURAL MODELING 208
4.4 SEQUENTIAL LOGIC 213
4.4.1 Registers 213
4.4.2 Resettable Registers 214
4.4.3 Enabled Registers 216
4.4.4 Multiple Registers 217
4.4.5 Latches 218
4.5 MORE COMBINATIONAL LOGIC 218
4.5.1 Case Statements 221
4.5.2 If Statements 222
4.5.3 Verilog casez 224
4.5.4 Blocking and Nonblocking Assignments 224
4.6 FINITE STATE MACHINES 229
4.7 PARAMETERIZED MODULES 234
4.8 TESTBENCHES 237
4.9 SUMMARY 241
Exercises 242
Verilog Exercises 247
VHDL Exercises 250
Interview Questions 253
Chapter 5 Digital Building Blocks 256
5.1 INTRODUCTION 256
5.2 ARITHMETIC CIRCUITS 256
5.2.1 Addition 256
5.2.2 Subtraction 263
5.2.3 Comparators 263
5.2.4 ALU 265
5.2.5 Shifters and Rotators 267
5.2.6 Multiplication 269
5.2.7 Division 270
5.2.8 Further Reading 271
5.3 NUMBER SYSTEMS 272
5.3.1 Fixed-Point Number Systems 272
5.3.2 Floating-Point Number Systems 273
5.4 SEQUENTIAL BUILDING BLOCKS 277
5.4.1 Counters 277
5.4.2 Shift Registers 278
5.5 MEMORY ARRAYS 280
5.5.1 Overview 280
5.5.2 Dynamic Random Access Memory 283
5.5.3 Static Random Access Memory (SRAM) 283
5.5.4 Area and Delay 284
5.5.5 Register Files 284
5.5.6 Read Only Memory 285
5.5.7 Logic Using Memory Arrays 287
5.5.8 Memory HDL 287
5.6 LOGIC ARRAYS 289
5.6.1 Programmable Logic Array 289
5.6.2 Field Programmable Gate Array 291
5.6.3 Array Implementations 296
5.7 SUMMARY 297
Exercises 299
Interview Questions 309
Chapter 6 Architecture 312
6.1 INTRODUCTION 312
6.2 ASSEMBLY LANGUAGE 313
6.2.1 Instructions 313
6.2.2 Operands: Registers, Memory, and Constants 315
6.3 MACHINE LANGUAGE 322
6.3.1 R-type Instructions 322
6.3.2 I-Type Instructions 324
6.3.3 J-type Instructions 325
6.3.4 Interpreting Machine Language Code 325
6.3.5 The Power of the Stored Program 326
6.4 PROGRAMMING 327
6.4.1 Arithmetic/Logical Instructions 327
6.4.2 Branching 331
6.4.3 Conditional Statements 333
6.4.4 Getting Loopy 334
6.4.5 Arrays 337
6.4.6 Procedure Calls 342
6.5 ADDRESSING MODES 350
6.6 LIGHTS, CAMERA, ACTION: COMPILING, ASSEMBLING, AND LOADING 353
6.6.1 The Memory Map 353
6.6.2 Translating and Starting a Program 354
6.7 ODDS AND ENDS 359
6.7.1 Pseudoinstructions 359
6.7.2 Exceptions 360
6.7.3 Signed and Unsigned Instructions 361
6.7.4 Floating-Point Instructions 363
6.8 REAL-WORLD PERSPECTIVE: IA-32 ARCHITECTURE 364
6.8.1 IA-32 Registers 365
6.8.2 IA-32 Operands 365
6.8.3 Status Flags 367
6.8.4 IA-32 Instructions 367
6.8.5 IA-32 Instruction Encoding 369
6.8.6 Other IA-32 Peculiarities 371
6.8.7 The Big Picture 372
6.9 SUMMARY 372
Exercises 374
Interview Questions 384
Chapter 7 Microarchitecture 386
7.1 INTRODUCTION 386
7.1.1 Architectural State and Instruction Set 386
7.1.2 Design Process 387
7.1.3 MIPS Microarchitectures 389
7.2 PERFORMANCE ANALYSIS 389
7.3 SINGLE-CYCLE PROCESSOR 391
7.3.1 Single-Cycle Datapath 391
7.3.2 Single-Cycle Control 397
7.3.3 More Instructions 400
7.3.4 Performance Analysis 403
7.4 MULTICYCLE PROCESSOR 404
7.4.1 Multicycle Datapath 405
7.4.2 Multicycle Control 411
7.4.3 More Instructions 418
7.4.4 Performance Analysis 420
7.5 PIPELINED PROCESSOR 424
7.5.1 Pipelined Datapath 427
7.5.2 Pipelined Control 428
7.5.3 Hazards 429
7.5.4 More Instructions 441
7.5.5 Performance Analysis 441
7.6 HDL REPRESENTATION 444
7.6.1 Single-Cycle Processor 445
7.6.2 Generic Building Blocks 449
7.6.3 Testbench 451
7.7 EXCEPTIONS 454
7.8 ADVANCED MICROARCHITECTURE 458
7.8.1 Deep Pipelines 458
7.8.2 Branch Prediction 460
7.8.3 Superscalar Processor 461
7.8.4 Out-of-Order Processor 464
7.8.5 Register Renaming 466
7.8.6 Single Instruction Multiple Data 468
7.8.7 Multithreading 469
7.8.8 Multiprocessors 470
7.9 REAL-WORLD PERSPECTIVE: IA-32 MICROARCHITECTURE 470
7.10 SUMMARY 476
Exercises 478
Untitled 484
Chapter 8 Memory Systems 486
8.1 INTRODUCTION 486
8.2 MEMORY SYSTEM PERFORMANCE ANALYSIS 490
8.3 CACHES 491
8.3.1 What Data Is Held in the Cache? 492
8.3.2 How Is the Data Found? 493
8.3.3 What Data Is Replaced? 501
8.3.4 Advanced Cache Design 502
8.3.5 The Evolution of MIPS Caches 506
8.4 VIRTUAL MEMORY 507
8.4.1 Address Translation 509
8.4.2 The Page Table 511
8.4.3 The Translation Lookaside Buffer 513
8.4.4 Memory Protection 514
8.4.5 Replacement Policies 515
8.4.6 Multilevel Page Tables 515
8.5 MEMORY-MAPPED I/O 517
8.6 REAL-WORLD PERSPECTIVE: IA-32 MEMORY AND I/O SYSTEMS 522
8.6.1 IA-32 Cache Systems 522
8.6.2 IA-32 Virtual Memory 524
8.6.3 IA-32 Programmed I/O 525
8.7 SUMMARY 525
EPILOGUE 526
Exercises 527
Interview Questions 535
Appendix A Digital System Implementation 538
A .1 INTRODUCTION 538
A.2 74XX LOGIC 538
A.2.1 Logic Gates 539
A.2.2 Other Functions 539
A.3 PROGRAMMABLE LOGIC 539
A.3.1 PROMs 539
A.3.2 PLAs 543
A.3.3 FPGAs 544
A.4 APPLICATION-SPECIFIC INTEGRATED CIRCUITS 546
A.5 DATA SHEETS 546
A.6 LOGIC FAMILIES 552
A.7 PACKAGING AND ASSEMBLY 554
A.8 TRANSMISSION LINES 557
A.8.1 Matched Termination 559
A.8.2 Open Termination 561
A.8.3 Short Termination 562
A.8.4 Mismatched Termination 562
A.8.5 When to Use Transmission Line Models 565
A.8.6 Proper Transmission Line Terminations 565
A.8.7 Derivation of Z0 567
A.8.8 Derivation of the Reflection Coefficient 568
A.8.9 Putting It All Together 569
A.9 ECONOMICS 570
Appendix B MIPS Instructions 574
Further Reading 578
Index 580

Produkt-Details

• Erscheint lt. Verlag: 26.7.2010
• Sprache: englisch
• Themenwelt: Sachbuch/Ratgeber
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Nachrichtentechnik
• ISBN-13: 9780080547060 / 9780080547060