Area Array Interconnection Handbook
Springer-Verlag New York Inc.
978-1-4613-5529-8 (ISBN)
Microelectronic packaging has been recognized as an important "enabler" for the solid state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later family or ceramics with matching expansivity to sili con and copper internal wiring was developed as a predecessor of the chip interconnection revolution in copper, multilevel, submicron wiring. Powerful server packages have been de veloped in which the combined chip and package copper wiring exceeds a kilometer. All of this was achieved with the constant objective of minimizing circuit delays through short, efficient interconnects.
1 History of Flip Chip and Area Array Technology.- 2 Wafer Bumping.- 3 Wafer-Level Test.- 4 Known Good Die (KGD).- 5 Wafer Finishing—Dicing, Picking, Shipping.- 6 Ceramic Chip Carriers.- 7 Laminate HDI Die Carriers.- 8 Flip-Chip Die Attach Technology.- 9 Solder Bump Flip-Chip Replacement Technology on Ceramic Carriers.- 10 Manufacturing Considerations and Tools for Flip Chip Assembly.- 11 Test and Burn-in Sockets.- 12 Underfill: The Enabling Technology for Flip-Chip Packaging.- 13 Reliability of Die-Level Interconnections.- 14 Ceramic and Plastic Pin Grid Array Technology.- 15 Plastic Ball Grid Array.- 16 Tape Ball Grid Array.- 17 Ceramic Ball and Column Grid Arrays.- 18 Chip Scale Package Technology.- 19 Assembly of Area Array Components.- 20 Area Array Component Replacement Technology.- 21 Product Connector Technology.- 22 Board-Level Area Array Interconnect Reliability.- 23 Chip Scale Package Assembly Reliability.- 24 Area-Array Design Principles.- 25 Area Array Leverages: Why and How to Choose a Package.- 26 Interconnections for High-Frequency Applications.- 27 Thermal Performance.- 28 Metallurgical Factors.- Contributing Authors.
| Zusatzinfo | CXXXVI, 1188 p. In 2 volumes, not available separately. |
|---|---|
| Verlagsort | New York, NY |
| Sprache | englisch |
| Maße | 178 x 254 mm |
| Themenwelt | Naturwissenschaften ► Biologie ► Ökologie / Naturschutz |
| Technik ► Elektrotechnik / Energietechnik | |
| Technik ► Maschinenbau | |
| ISBN-10 | 1-4613-5529-X / 146135529X |
| ISBN-13 | 978-1-4613-5529-8 / 9781461355298 |
| Zustand | Neuware |
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