CMOS Processors and Memories (eBook)

Krzysztof Iniewski (Herausgeber)

eBook Download: PDF

2010
VI, 382 Seiten
Springer Netherland (Verlag)
978-90-481-9216-8 (ISBN)

Infos

CMOS Processors and Memories addresses the-state-of-the-art in integrated circuit design in the context of emerging computing systems. New design opportunities in memories and processor are discussed. Emerging materials that can take system performance beyond standard CMOS, like carbon nanotubes, graphene, ferroelectrics and tunnel junctions are explored.

CMOS Processors and Memories is divided into two parts: processors and memories. In the first part we start with high performance, low power processor design, followed by a chapter on multi-core processing. They both represent state-of-the-art concepts in current computing industry. The third chapter deals with asynchronous design that still carries lots of promise for future computing needs. At the end we present a 'hardware design space exploration' methodology for implementing and analyzing the hardware for the Bayesian inference framework. This particular methodology involves: analyzing the computational cost and exploring candidate hardware components, proposing various custom architectures using both traditional CMOS and hybrid nanotechnology CMOL. The first part concludes with hybrid CMOS-Nano architectures.

The second, memory part covers state-of-the-art SRAM, DRAM, and flash memories as well as emerging device concepts. Semiconductor memory is a good example of the full custom design that applies various analog and logic circuits to utilize the memory cell's device physics. Critical physical effects that include tunneling, hot electron injection, charge trapping (Flash memory) are discussed in detail. Emerging memories like FRAM, PRAM and ReRAM that depend on magnetization, electron spin alignment, ferroelectric effect, built-in potential well, quantum effects, and thermal melting are also described.

CMOS Processors and Memories is a must for anyone serious about circuit design for future computing technologies. The book is written by top notch international experts in industry and academia. It can be used in graduate course curriculum.

Krzysztof (Kris) Iniewski is managing R&D at Redlen Technologies Inc., a start-up company in British Columbia. His research interests are in VLSI circuits for medical and security applications. He is also an executive director of CMOS Emerging Technologies (www.cmoset.com). From 2004 to 2006 he was an Associate Professor at the Electrical Engineering and Computer Engineering Department of University of Alberta where he conducted research on low power wireless circuits and systems. During his tenure in Edmonton he put together a book for CRC Press 'Wireless Technologies: Circuits, Systems and Devices'. From 1995 to 2003, he was with PMC-Sierra and held various senior technical and management positions. Prior to joining PMC-Sierra, from 1990 to 1994 he was an Assistant Professor at the University of Toronto's Electrical Engineering and Computer Engineering. Dr. Iniewski has published over 100 research papers in international journals and conferences. He holds 18 international patents granted in USA, Canada, France, Germany, and Japan. He received his Ph.D. degree in electronics (honors) from the Warsaw University of Technology (Warsaw, Poland) in 1988. Together with Carl McCrosky and Dan Minoli he is an author of 'Data Networks - VLSI and Optical Fibre', Wiley, 2008. He recently edited 'Medical Imaging Electronics', Wiley 2009, 'VLSI Circuits for Bio-medical applications', Artech House 2008, and 'Circuits at Nanoscale: Communications, Imaging and Sensing', CRC Press 2008.

Inhalt

Contents 6
Part I:Processors 8
Chapter 1: Design of High Performance Low Power Microprocessors 9
1.1 Introduction 10
1.2 Concurrent Multi-threading (CMT) 10
1.3 Power and Power Management 11
1.3.1 Dynamic Power 11
1.3.1.1 Activity Factor and Switching Capacitance 12
1.3.1.2 Voltage (VDD) and Frequency of Operation 13
1.3.1.3 Crowbar Power 14
1.3.2 Static (Leakage) Power 14
1.3.2.1 Sub-threshold Leakage 14
1.3.2.2 Gate Leakage 15
1.3.2.3 Diode Leakage 15
1.3.2.4 Effect of VDD and Temperature on Leakage 16
1.3.2.5 Back Bias 18
1.3.3 Using VDD and Back-Bias to Optimize for Performance and Power 18
1.3.4 Power Management: What and How? 20
1.3.4.1 Dynamic Voltage and Frequency Scaling 20
1.3.4.2 Other Power Management Techniques 22
1.4 Clock Design 23
1.4.1 Clock Skew/Clock Uncertainty 26
1.4.1.1 Sources of Clock Skew/Clock Uncertainty 26
1.5 Memory Design 27
1.5.1 The 6-T Memory Cell 28
1.5.1.1 Important Metrics/Tests for Evaluating a 6-T Memory Cell 29
1.5.2 Memory Redundancy 30
1.5.3 The Importance of Statistical Analysis 30
1.6 Process Technology and Impact of Layout on Performance and Power 31
1.7 Conclusion 32
References 32
Chapter 2: Towards High-Performance and Energy-Efficient Multi-core Processors 34
2.1 Motivating Multi-core Processors 34
2.1.1 Challenges on Uni-core Processors 34
2.1.1.1 High Performance Innovations are Challenging 35
2.1.1.2 Power Dissipation Becomes the Key Constraint 35
2.1.1.3 The Gap Between Dream and Reality on Performance and Energy Efficiency 37
2.1.1.4 Future Fabrication Technologies Imposing New Challenges 37
2.1.2 Challenges on ASIC Implementations 38
2.1.3 Solution: Multi-core Processors 39
2.2 Pioneering Multiprocessor Systems and Multi-core Processors 41
2.2.1 Communication Model: Shared-Memory and Message Passing 41
2.2.2 Interconnect Topology 42
2.2.3 Some Design Cases 42
2.3 Modern Multi-core Processors 43
2.3.1 Design Cases of Modern Multi-core Processors 44
2.3.2 Distinguishing Multi-core Processors 48
2.4 Looking Forward to the Future of Multi-core Processors 51
2.4.1 There is no Universal Multi-core Processor 51
2.4.2 Fault-Tolerance Will Become a Key Issue in Multi-core Processors 52
Reference 53
Chapter 3: Low Power Asynchronous Circuit Design: An FFT/IFFT Processor 57
3.1 Introduction 57
3.2 Synchronization: Synchronous and Asynchronous 58
3.2.1 Synchronous Approach 59
3.2.2 Asynchronous Approach 60
3.2.2.1 Delay Models 61
3.2.2.2 Handshaking Protocols and Channels 61
3.2.2.3 Data Encoding 64
3.2.2.4 Asynchronous Pipelines 64
3.3 Low Power Asynchronous Micro/Macro Cells 65
3.3.1 Latch Adder 65
3.3.2 Asynchronous Carry Completion Sensing Adders 68
3.3.3 Multiplier 75
3.3.4 Memory 82
3.4 Low Power Asynchronous FFT/IFFT Processor 84
3.4.1 FFT/IFFT Algorithm 85
3.4.2 Benchmarked Synchronous FFT/IFFT Processor 86
3.4.3 Asynchronous FFT/IFFT Processor 87
3.4.4 Comparison of the Synchronous and Asynchronous Designs 92
3.5 Conclusions 97
References 98
Chapter 4: CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price 100
4.1 Introduction 101
4.2 Hardware for Computational Models 103
4.2.1 Hardware Virtualization Spectrum 103
4.2.2 Existing Hardware Implementations of George and Hawkins’ Model 104
4.2.3 Hardware Design Space Exploration: An Architecture Assessment Methodology 105
4.3 A Bayesian Memory (BM) Module 105
4.4 Hardware Architectures for Bayesian Memory 109
4.4.1 Definition of Hardware Architectures for BM 109
4.4.2 General Issues 111
4.4.2.1 Precision/Bits 111
4.4.2.2 Communication 112
4.4.2.3 Number of Parent and Child BMs, and Code Book (CB) Size 112
4.4.2.4 Virtualization 113
4.4.2.5 Hybrid Nanotechnology – CMOL 113
4.5 Digital CMOS and CMOL Hardware Architectures for Bayesian Memory (BM) 114
4.5.1 Floating-Point (FLP) Architecture 115
4.5.2 Logarithmic Number System (LNS) Architecture 116
4.5.3 Fixed-Point (FXP) Architecture 116
4.6 Mixed-Signal (MS) CMOS and CMOL Hardware Architectures for Bayesian Memory (BM) 118
4.6.1 Mixed-Signal CMOS Architecture 119
4.6.2 Mixed-Signal CMOL Architecture 121
4.7 Performance/Price Analysis and Results 122
4.7.1 Performance/Price Analysis 122
4.7.2 Performance/Price Results and Discussion 124
4.7.3 Scaling Estimates for BM Based Cortex-Scale System 129
4.8 Conclusion, Contribution and Future Work 131
4.9 Appendix 132
4.9.1 Digital FLP or LNS Architecture 132
4.9.1.1 Time 132
4.9.1.2 Area 133
4.9.1.3 Power 133
4.9.2 Digital FXP Architecture 133
4.9.2.1 Time 133
4.9.2.2 Area 134
4.9.2.3 Power 134
4.9.3 Mixed-Signal CMOS Architecture 135
4.9.3.1 Time 135
4.9.3.2 Area 135
4.9.3.3 Power 135
4.9.4 Mixed-Signal CMOL Architecture 136
4.9.4.1 MS CMOL Nanogrid for the SVMM 136
4.9.4.2 Time 136
4.9.4.3 Area 137
4.9.4.4 Power 137
4.9.5 Example: Use of Architecture Assessment Methodology for Associative Memory Model 137
References 139
Chapter 5: A Hybrid CMOS-Nano FPGA Based on Majority Logic: From Devices to Architecture 142
5.1 Introduction 142
5.2 Nanoscale Technologies and Devices 144
5.2.1 Nanoscale Switches and the Crossbar Array 144
5.2.1.1 Nanoscale Switches 145
Self Assembled Molecular Electronics 145
Phase Change Devices 146
Generic MRAM Device 146
Metal Oxide Device 148
5.2.1.2 Resonant Tunneling Diodes 148
5.2.2 Fundamental Circuits 150
5.2.2.1 Crossbar Array 150
5.2.2.2 Programmable Logic Array (PLA) 150
5.2.2.3 Goto Pair 151
5.2.3 Device Modelling 152
5.3 The Programmable Majority Logic Array 154
5.4 A CMOS-Nano PMLA Based FPGA 157
5.4.1 Partitioning Logic Between CMOS and Nano 158
5.4.1.1 All Nano PMLA Mapping 158
5.4.1.2 Equal Partitioning Between CMOS and Nano 159
5.4.2 Results and Comparisons 159
5.4.3 Impact: Considerations for Designing CMOS/Nano Circuits 160
5.5 Future Prospects (Memristors) 161
5.6 Summary 162
References 162
Part II:Memories 165
Chapter 6: Memory Systems for Nano-computer 166
6.1 Introduction 166
6.1.1 The Value of a Computer 166
6.1.2 The Origin of a Computer Body 167
6.1.3 The Birth of a Memory Device 168
6.1.4 The Brief on a Computer System 169
6.1.5 The Brief on a Memory Hierarchy 169
6.2 Memory Devices and Circuits 170
6.2.1 The Foundation of a Memory Core 170
6.2.2 The Foundation of a Memory Design 173
6.2.2.1 Analog Circuits for a Memory Device 173
6.2.2.2 Logic Circuits for a Memory Device 179
6.2.3 The Brief on the Interconnect Issues 182
6.3 Memory Hierarchy and Hardware Compositions 182
6.3.1 The Types of Memories 182
6.3.2 The Memory Architectures 183
6.3.3 The Brief on a Memory Controller 185
6.3.4 The Memory Hierarchy 185
6.3.5 The Future of the Memory Hierarchy 187
6.3.6 The Device-Level Innovations 188
6.4 Software Interfaces of Memory Devices 189
6.4.1 The Memory as a System Resource 189
6.4.2 The Software Overhead in a Memory-related Performance 191
6.4.3 The Future Computing System 191
6.4.3.1 Evolution of a Memory System 191
6.4.3.2 Evolution of a Storage System 192
6.5 The Top-down Approach: Wrap-up 193
6.6 Conclusion 194
References 195
Chapter 7: Flash Memory 198
7.1 Introduction to Flash Memory 198
7.1.1 Introduction 198
7.1.2 Semiconductor Memory 199
Non-Volatile Memory 200
7.1.3 Flash Memory 200
7.2 Flash Memory Architecture 202
7.2.1 Chip Architecture 202
7.2.2 Basic Operating Principles of Flash-Cell 205
7.2.3 Memory Array Architecture 206
7.2.4 Program Operation 208
7.2.5 Erase Operation 211
7.2.6 Read Operation 214
7.3 MLC Technology 217
7.3.1 Concept of MLC Technology 217
7.3.2 Precise Charge Placement in MLC Technology 217
7.3.3 Precise Charge Sensing in MLC Technology 220
7.4 Flash Memory Reliability 223
7.4.1 Endurance 223
7.4.2 Data Retention 225
7.5 Flash Memory Scaling 227
7.5.1 Cell Scaling Issues 227
7.5.2 Alternative Method for High Density 230
7.6 Conclusions 231
References 231
Chapter 8: CMOS-based Spin-Transfer Torque Magnetic Random Access Memory (ST–MRAM) 234
8.1 Introduction 235
8.2 CMOS-based ST–MRAM Elements 236
8.2.1 Background 236
8.2.2 Current Issues 240
8.3 Magnetization Dynamics in ST–MRAM Elements 241
8.3.1 Method of Micromagnetic Modeling 242
8.3.2 Spin-Polarized Current Pulse Switching of Ni80Fe20/Cu/Co Nanopillar Elements 242
8.3.3 Fabrication and Characterization of Prototype ST–MRAM 247
8.3.3.1 Fabrication of 8 × 8 Array of ST–MRAM Nanopillar Elements 247
8.3.3.2 Characterization of ST–MRAM Nanopillar Elements 247
8.4 Conclusions 250
References 251
Chapter 9: Magnetization Switching in Spin Torque Random Access Memory: Challenges and Opportunities 254
9.1 Introduction to Spin Torque Random Access Memory 255
9.2 Magnetization Switching Challenges as SPRAM Scales Down 256
9.3 SPRAM Device Characterization and System Scaling Down Requirement 260
9.3.1 Characterization of Spin Torque Induced Magnetization Switching 260
9.3.2 SPRAM System Dynamic Modeling 266
9.3.3 SPRAM Scale Down Requirments 269
9.4 Reasearch and Development Opportunities for Switching Current Reduction and Variability Control 273
9.4.1 Current Reduction Through Changing Magnetic Properties 273
9.4.2 Current Reduction Through Decreasing Damping by Changing Interfacial Tunneling Properties 275
9.4.3 Current Reduction Through Increasing Spin Torque Efficiency 278
9.4.4 Currnt Reduction Through Time and Spatial Varying Polarized Current 281
9.4.5 Current Reduction Through Coupled Magnetic Elements and Nonunifrom Magnetization Switching 284
9.4.6 Current Reduction Through Thermal Spin Torque Switching 286
9.4.7 Variability Control at Device Level 287
9.4.8 Variability Control at System Level 291
References 293
Chapter 10: High Performance Embedded Dynamic Random Access Memory in Nano-Scale Technologies 296
10.1 Introduction 296
10.2 Evolution for High Performance Embedded DRAMs 297
10.3 Principles of High Performance Embedded DRAM Technology, Architecture, and Designs 299
10.3.1 Technology 299
10.3.2 Macro Architecture 301
10.3.3 Modes of Operation 304
10.3.3.1 Single Bank Fast Random Access Cycle Mode 304
10.3.3.2 Multi Bank Pipeline Mode 306
10.3.4 Wordline Architectures 307
10.3.5 Bitline Architectures 309
10.3.6 Sensing Schemes 310
10.3.7 Late Write, Early Write, and Direct Write 312
10.3.8 Negative Wordline Architecture 312
10.3.9 Concurrent Refresh Mode 313
10.3.10 Redundancy 314
10.3.11 Test Methodology 316
10.4 IBM Embedded DRAM Macros 316
10.4.1 Embedded DRAMs for ASIC 317
10.4.2 Embedded DRAM with Destructive Read Architecture 319
10.4.3 Embedded DRAM for High-performance SOI Microprocessor 320
10.5 High Performance Cache with Embedded DRAM Macros 323
10.5.1 Architecture 323
10.5.2 ABIST and FAR 324
10.5.3 Refresh Management 325
10.6 Future Work 327
10.6.1 Embedded DRAM with Floating Body Cell 327
10.6.2 Embedded DRAM with Gain Cell 328
10.6.3 Embedded DRAM with Twin Cell 330
10.6.4 Embedded DRAM for 3 Dimensional Integration 331
10.6.5 Summary 333
References 334
Chapter 11: Timing Circuit Design in High Performance DRAM 338
11.1 Introduction 338
11.1.1 Memory Interface 338
11.1.2 Evolution of the DRAM Interface and Timing Specifications 339
11.1.3 Source-Synchronous Interface and Matched Routing 340
11.1.4 Timing Adjust Circuitry 341
11.2 Clock Distribution Network 342
11.2.1 CML Versus CMOS 342
11.2.2 Clock Division and Multiphase Clocking 344
11.2.3 Voltage and Temperature Insensitive CDN 345
11.2.4 Self-adaptive Bias Generator 347
11.2.5 Simulation Results 348
11.3 Clock Synchronization Circuits 349
11.3.1 MDLL Clocking Architecture 349
11.3.2 Fast-Lock Digital DLL 351
11.3.3 Analog Phase Generator (APG) 353
11.3.4 Measurement Results 355
11.3.5 Other Consideration 357
11.4 Future Directions for Nanoscaled DRAM Interface 359
References 360
Chapter 12: Overview and Scaling Prospect of Ferroelectric Memories 362
12.1 Introduction 362
12.2 FeRAM Principle and Read/Write Mechanism 363
12.3 Conventional 1T/1C FeRAM and Current Memory Cell Structures 365
12.4 Chain FeRAM Architecture and Development History 366
12.5 Scaling Techniques to Reduce Bitline Capacitance 368
12.6 Dummy Cell Design Techniques 371
12.7 Cell Signal Enhancement Techniques 372
12.8 Reliability Issues 374
12.9 Future Prospect of FeRAMs – 3D Capacitor and New FeRAM 375
12.10 Application as Nonvolatile FeRAM Cache 377
12.11 Conclusions 379
References 379

Produkt-Details

• Erscheint lt. Verlag: 9.8.2010
• Reihe/Serie: Analog Circuits and Signal Processing
• Reihe/Serie: Analog Circuits and Signal Processing
• Zusatzinfo: VI, 382 p.
• Verlagsort: Dordrecht
• Sprache: englisch
• Themenwelt: Naturwissenschaften ► Chemie ► Analytische Chemie
• Themenwelt: Naturwissenschaften ► Physik / Astronomie ► Festkörperphysik
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Themenwelt: Technik ► Nachrichtentechnik
• Schlagworte: Analog VLSI • Carbon Nanotubes • CMOS • Digital VLSI • DRAM • field programmable gate array • FPGA • Graphen • Hardware • Integrated circuit • Material • nanoelectronics • nano-scale • nanotechnology • Nanotube • Physics • semiconductor • SRAM
• ISBN-10: 90-481-9216-1 / 9048192161
• ISBN-13: 978-90-481-9216-8 / 9789048192168