Machine Learning Systems

The Role of Hardware Design for High Performance Computing

Shanshan Liu, Pedro Reviriego, Zhen Gao, Fabrizio Lombardi (Herausgeber)

Buch | Hardcover

2026
Springer International Publishing (Verlag)
9783032174451 (ISBN)

Infos

This book addresses the technological contributions and developments of advanced hardware for Machine Learning (ML) computing systems. The authors discuss state-of-the-art progress in this area (and related topics) as well as reporting on their application to diverse fields. This is achieved by chapters covering the entire spectrum of research activities to include design and applications, with a focus on high performance and dependable operation. The entire hardware stack (from circuit, to architecture, up to the system level) is discussed in detail.  The book will cover innovative material as well as tutorials, reviews and surveys of current theoretical/experimental results, design methodologies and applications over a wide spectrum of scope for an enlarged readership, so to include engineers as well as scientists.

Autor

Shanshan Liu is currently a professor with the School of Information and Communication Engineering, University of Electronic Science and Technology of China, Chengdu, China. She received the Ph.D. degree in Microelectronics and Solid-State Electronics from Harbin Institute of Technology, Harbin, China, in 2018. From 2018 to 2021, she was a post-doctoral researcher with the Department of Electrical and Computer Engineering, Northeastern University, Boston, USA, and then an assistant professor with the Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, USA from 2021 to 2023.Her research interests include fault tolerant design in high performance computing systems, emerging computing, VLSI design, dependable machine learning, and error correction codes. She has published more than 100 peer-reviewed papers in these areas. She is a Member-at-Large of the IEEE Nanotechnology Council, an Associate Editor for the IEEE Transactions on Emerging Topics in Computing and the IEEE Transactions on Nanotechnology, and a Guest Editor for the IEEE Transactions on Circuits and Systems I: Regular Papers. She also serves as an organization committee member or a technical program committee member for several IEEE/ACM conferences such as NANO, NMDC, DFT, IOLTS, ICCAD, GLSVLSI.

Pedro Reviriego completed the PhD in 1997 and joined the R&D department of Teldat a Spanish company that designs and manufactures routers. Then in 2000, he moved to an Irish start-up that was developing Ethernet transceiver ASICs and later acquired by an US company (now part of Broadcom). The transceivers developed were licensed to Intel and had a large commercial success. Since 2007 he has been in Academia with positions at Nebrija University, Universidad Carlos III de Madrid and currently, Universidad Politécnica de Madrid. Dr. Reviriego has made significant contributions in different areas like Energy Efficiency in Ethernet on which he was a pioneer contributing to the IEEE 802.3 standards and writing seminal papers on the field with more than 470 citations in Google Scholar. This work was recognized with two Google Research Awards. The second topic on which he has worked is the design and implementation of Error Correction Codes (ECCs) to protect memories. In this area, he has pioneered the use of one step majority logic decodable codes for memory protection with many publications. More recently, he has focused on fault-tolerant machine learning; in this area he has proposed fault tolerant implementations for many machine learning algorithms, including complex neural networks.Dr. Reviriego is associate editor of IEEE Transactions on Emerging Topics in Computing and has published more than 300 papers on journals indexed on JCR, most of them in IEEE Transactions with more than 6700 citations on Google Scholar. He also holds more than 12 US patents, most of them in collaboration with NVIDIA/Mellanox.

Zhen Gao received the BS, MS and PhD degree in Electrical Engineering from Tianjin University, China, in 2005, 2007 and 2011, respectively. He was a visiting scholar at Georgia Tech from 2008 to 2010, and a Postdoc researcher in Tsinghua University from 2011 to 2014. He is currently an Associate Professor in Tianjin University. His research interests include circuit reliability, fault tolerant design and software defined radios. He has published more than 100 peer-reviewed papers in these areas. He won the best paper award of DFT2021 and the CCF Fault Tolerant Computing Outstanding Achievement Award in 2025.Dr. Gao is the Senior Member of IEEE, the Chinese Institute of Electronics (CIE) and the China Institute of Communications (CIC), and the Executive Committee of the Fault Tolerant Special Committee of China Computer Federation (CCF).

Fabrizio Lombardi graduated in 1977 from the University of Essex (UK) with a B.Sc. (Hons.) in Electronic Engineering. In 1977 he joined the Microwave Research Unit at

Inhalt

High performance machine learning accelerators on fpga.- Floating point arithmetic in deep neural networks evaluation and implementation of conventional and emerging formats with mixed precision strategies.- High performance computing architectures for ml.- High performance domain specific computing architectures for machine learning.- Edge ai training accelerator design.- Accelerating machine learning with unconventional architectures.- Mram based energy efficient computing architectures for accelerators machine learning.- Energy efficient data aware computation in computing in memory architecture.- Stochastic computing applied to morphological neural networks.- Approximate multipliers for machine learning applications.- Edge computing meets giant ai innovations in large language model efficiency.- Chiplet based accelerator design for scalable training of transformer based generative adversarial networks.- Energy consumption in generative ai insights from large language models inference.- Sustainable and responsible generative artificial intelligence gen ai a survey.- Low power machine learning realization techniques on biomedical wearable devices.- Application of algorithm and hardware co design in the hardware accelerator of visual slam frontend.- Application of algorithm and hardware co design in the hardware accelerator of visual slam backend.- Hardware efficient designs for spiking neural networks.

Produkt-Details

• Erscheint lt. Verlag: 6.4.2026
• Zusatzinfo: Approx. 450 p. 100 illus. in color.
• Verlagsort: Cham
• Sprache: englisch
• Maße: 155 x 235 mm
• Themenwelt: Informatik ► Theorie / Studium ► Künstliche Intelligenz / Robotik
• Themenwelt: Informatik ► Weitere Themen ► Hardware
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Advanced Architectures for Machine Learning • Dependability in Machine Learning Hardware • machine learning hardware • Machine Learning with Large Language Models • Security and Trust in Machine Learning Hardware
• ISBN-13: 9783032174451 / 9783032174451
• Zustand: Neuware