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Very-Large-Scale Integration Physical Design

Engineering Change Order and Timing Design Rule Check
Buch | Hardcover
176 Seiten
2025 | Unabridged edition
Cambridge Scholars Publishing (Verlag)
978-1-0364-4053-4 (ISBN)
CHF 116,95 inkl. MwSt
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This book presents an innovative approach to rectify Timing-Design Rule Check (TDRC) violations in Very-Large-Scale Integration (VLSI) chip design. Through the utilization of Tool Command Language (TCL) scripting, this automated solution streamlines the Engineering Change Order (ECO) process, offering efficiency, accuracy, and accessibility. By incorporating various strategies such as cell up-sizing, low threshold voltage cell swapping, and buffer insertion, the authors tackle TDRC violations with precision. Their methodology integrates a slope violation percentage-based guide and net length-based buffer insertion strategy, tailored to address specific violations effectively. Moreover, the proactive integration of a Non-Linear Delay Model (NLDM) look-up table ensures robust timing optimization, preventing hold timing violations. This comprehensive guide navigates fundamental placement rules and ECO implementation, featuring a two-step approach named 'make shorts into opens' to resolve violations efficiently. Impressively, the automated TDRC Fixer achieves an 87% TDRC violation fix rate with minimal global timing shifts, showcasing the effectiveness of TCL scripting in VLSI physical design workflows. This book is a must-read for professionals, researchers, and students seeking to enhance their understanding of VLSI chip design methodologies and optimize their ECO workflows with pragmatic and accessible solutions.

Kim Ho Yeap, an associate professor at Universiti Tunku Abdul Rahman, Malaysia, and a senior member of the Institute of Electrical and Electronics Engineers, has published about 180 peer-reviewed articles and 3 patents. One of his published works impacted the design of Atacama Large Millimeter Array radio telescope's receiver optics. Yeap holds Chartered Engineer, Professional Engineer, and Association of Southeast Asian Nations Chartered Professional Engineer statuses, received teaching excellence and Intel Kudos awards, and secured 25 research grants.Ing Ming Tan holds a Bachelor's degree with Honours in Electronic Engineering and a Master of Engineering Science from Universiti Tunku Abdul Rahman. Presently, he serves as a design engineer at Intel Microelectronics.

Erscheinungsdatum
Verlagsort Newcastle upon Tyne
Sprache englisch
Maße 148 x 212 mm
Themenwelt Mathematik / Informatik Informatik Theorie / Studium
Technik Elektrotechnik / Energietechnik
ISBN-10 1-0364-4053-2 / 1036440532
ISBN-13 978-1-0364-4053-4 / 9781036440534
Zustand Neuware
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