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Microprocessor Architectures

RISC, CISC and DSP

Steve Heath (Autor)

Buch | Softcover

400 Seiten

1995 | 2nd Revised edition
Butterworth-Heinemann Ltd (Verlag)
978-0-7506-2303-2 (ISBN)

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An updated edition reflecting the changes in the industry. Based on several years of involvement with users who have gone through the decision-making process and who have frequently asked many questions, this book covers in-depth RISC, CISC and DSP microprocessor architectures.

Complex instruction set computers; 32 bit CISC processors; the RISC challenge; RISC wars; digital signal processors; memory, memory management and caches; real time software, interrupts and exceptions; multiprocessing; application examples; semiconductor technology; the changing design cycle; the next generations; selecting a microprocessor architecture; "lies, damn lies and benchmarks"; alternative microprocessor architectures.

Erscheint lt. Verlag	31.3.1995
Zusatzinfo	200 line drawings, index
Verlagsort	Oxford
Sprache	englisch
Maße	156 x 234 mm
Gewicht	628 g
Themenwelt	Mathematik / Informatik ► Informatik ► Theorie / Studium
ISBN-10	0-7506-2303-9 / 0750623039
ISBN-13	978-0-7506-2303-2 / 9780750623032
Zustand	Neuware