System Level Design from HW/SW to Memory for Embedded Systems

5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3–6, 2015, Proceedings

Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, Achim Rettberg (Herausgeber)

Buch | Softcover

XII, 231 Seiten

2018
Springer International Publishing (Verlag)
9783030079178 (ISBN)

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This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015.

The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.

Erscheint lt. Verlag	11.12.2018
Reihe/Serie	IFIP Advances in Information and Communication Technology
Zusatzinfo	XII, 231 p. 92 illus.
Verlagsort	Cham
Sprache	englisch
Maße	155 x 235 mm
Gewicht	379 g
Themenwelt	Informatik ► Theorie / Studium ► Künstliche Intelligenz / Robotik
Schlagworte	Applied Computing • bandwidth • Computer Architecture • Cyber-Physical Systems • Embedded Systems • Field Programmable Gate Array (FPGA) • Image Processing • many-core systems • Microprocessor chips • Model Checking • multicore systems • Semantics • Software engineering • Specifications • verification
ISBN-13	9783030079178 / 9783030079178
Zustand	Neuware