FPGA Prototyping by VHDL Examples (eBook)

Xilinx MicroBlaze MCS SoC

Pong P. Chu (Autor)

eBook Download: PDF

2017 | 2. Auflage
John Wiley & Sons (Verlag)
978-1-119-28275-4 (ISBN)

Infos

A hands-on introduction to FPGA prototyping and SoC design

This Second Edition of the popular book follows the same 'learning-by-doing' approach to teach the fundamentals and practices of VHDL synthesis and FPGA prototyping. It uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow strict design guidelines and coding practices used for large, complex digital systems.

The new edition is completely updated. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software 'programmability' and develop complex and interesting embedded system projects. The revised edition:

• Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I²C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
• Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelop generator.
• Expands the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
• Introduces basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
• Provides an overview of bus interconnect and interface circuit.
• Introduces basic embedded system software development.
• Suggests additional modules and peripherals for interesting and challenging projects.

The FPGA Prototyping by VHDL Examples, Second Edition makes a natural companion text for introductory and advanced digital design courses and embedded system course. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.

PONG P. CHU, PhD is Associate Professor in the Department of Electrical Engineering and Computer Science at Cleveland State University, Cleveland, Ohio. He has taught undergraduate and graduate digital systems and computer architecture courses for more than two decades, and has received multiple instructional grants from the National Science Foundation.

Inhalt

FPGA PROTOTYPING BY VHDL EXAMPLES 3
CONTENTS 9
Preface 27
Acknowledgments 33
PART I BASIC DIGITAL CIRCUITS DEVELOPMENT 35
1 Gate-Level Combinational Circuit 37
1.1 Overview of VHDL 37
1.2 General description 38
1.2.1 Basic lexical rules 39
1.2.2 Library and package 39
1.2.3 Entity declaration 39
1.2.4 Data type and operators 39
1.2.5 Architecture body 40
1.2.6 Code of a 2-bit comparator 41
1.3 Structural description 42
1.4 Top-level signal mapping 44
1.5 Testbench 45
1.6 Bibliographic notes 47
1.7 Suggested experiments 47
1.7.1 Code for gate-level greater-than circuit 47
1.7.2 Code for gate-level binary decoder 47
2 Overview of FPGA and EDA Software 49
2.1 FPGA 49
2.1.1 Overview of a general FPGA device 49
2.1.2 Overview of the Xilinx Artix-7 devices 50
2.2 Overview of the Digilent Nexys 4 DDR board 51
2.3 Development flow 52
2.4 Xilinx Vivado Design Suite 54
2.5 Bibliographic notes 54
2.6 Suggested experiments 54
2.6.1 Gate-level greater-than circuit 54
2.6.2 Gate-level binary decoder 56
3 RT-Level Combinational Circuit 59
3.1 RT-level components 59
3.1.1 Relational operators 61
3.1.2 Arithmetic operators 61
3.1.3 Other synthesis-related VHDL constructs 63
3.1.4 Summary 64
3.2 Routing circuit with concurrent assignment statements 65
3.2.1 Conditional signal assignment statement 65
3.2.2 Selected signal assignment statement 68
3.3 Modeling with a process 70
3.3.1 Process 70
3.3.2 Sequential signal assignment statement 71
3.4 Routing circuit with if and case statements 72
3.4.1 If statement 72
3.4.2 Case statement 73
3.4.3 Comparison to concurrent statements 75
3.4.4 Unintended memory 76
3.5 Constants and generics 77
3.5.1 Constants 77
3.5.2 Generics 79
3.6 Replicated structure 80
3.6.1 Loop statements 80
3.6.2 Example 81
3.7 Design examples 82
3.7.1 Hexadecimal digit to seven-segment LED decoder 82
3.7.2 Sign-magnitude adder 86
3.7.3 Barrel shifter 89
3.7.4 Simplified floating-point adder 90
3.8 Bibliographic notes 94
3.9 Suggested experiments 94
3.9.1 Multi-function barrel shifter 94
3.9.2 Parameterized barrel shifter 94
3.9.3 Dual-priority encoder 95
3.9.4 BCD incrementor 95
3.9.5 Floating-point greater-than circuit 95
3.9.6 Floating-point and signed integer conversion circuit 95
3.9.7 Enhanced floating-point adder 96
4 Regular Sequential Circuit 97
4.1 Introduction 97
4.1.1 D FF and register 98
4.1.2 Basic block system 98
4.1.3 Code development 99
4.1.4 Sequential circuit coding style 99
4.2 HDL code of the FF and register 100
4.2.1 D FF 100
4.2.2 Register 103
4.3 Simple design examples 104
4.3.1 Shift register 104
4.3.2 Binary counter and variant 105
4.4 Testbench for sequential circuits 108
4.5 Case study 111
4.5.1 LED time-multiplexing circuit 112
4.5.2 Stopwatch 119
4.6 Timing and clocking 123
4.6.1 Timing of FF 123
4.6.2 Maximum operating frequency 124
4.6.3 Clock tree 125
4.6.4 GALS system and CDC 126
4.7 Bibliographic notes 127
4.8 Suggested experiments 127
4.8.1 Programmable square wave generator 127
4.8.2 PWM and LED dimmer 127
4.8.3 Rotating square circuit 127
4.8.4 Heartbeat circuit 128
4.8.5 Rotating LED banner circuit 128
4.8.6 Enhanced stopwatch 128
5 FSM 129
5.1 Introduction 129
5.1.1 Mealy and Moore outputs 130
5.1.2 FSM representation 130
5.2 FSM code development 133
5.3 Design examples 136
5.3.1 Rising-edge detector 136
5.3.2 Debouncing circuit 140
5.3.3 Testing circuit 144
5.4 Bibliographic notes 146
5.5 Suggested experiments 146
5.5.1 Dual-edge detector 146
5.5.2 Early detection debouncing circuit 146
5.5.3 Parking lot occupancy counter 146
6 FSMD 149
6.1 Introduction 149
6.1.1 Single RT operation 150
6.1.2 ASMD chart 150
6.1.3 Decision box with a register 152
6.2 Code development of an FSMD 155
6.2.1 Debouncing circuit based on RT methodology 155
6.2.2 Code with explicit data path components 155
6.2.3 Code with implicit data path components 158
6.2.4 Comparison 159
6.3 Design examples 161
6.3.1 Fibonacci number circuit 161
6.3.2 Division circuit 164
6.3.3 Binary-to-BCD conversion circuit 167
6.3.4 Period counter 170
6.3.5 Accurate low-frequency counter 173
6.4 Bibliographic notes 177
6.5 Suggested experiments 177
6.5.1 Early detection debouncing circuit 177
6.5.2 BCD-to-binary conversion circuit 177
6.5.3 Fibonacci circuit with BCD I/O: design approach 1 177
6.5.4 Fibonacci circuit with BCD I/O: design approach 2 178
6.5.5 Auto-scaled low-frequency counter 178
6.5.6 Reaction timer 179
6.5.7 Babbage difference engine emulation circuit 179
7 RAM and Buffer of FPGA 181
7.1 Embedded memory of FPGA device 181
7.1.1 Memory of an Artix device 182
7.1.2 Memory available in a Nexys 4 DDR board 182
7.2 General description for a RAM-like component 183
7.2.1 Register file 183
7.2.2 Dynamic array indexing operation 185
7.2.3 Key aspects of a RAM module 187
7.2.4 Genuine ROM 187
7.3 FIFO buffer 189
7.3.1 FIFO read configuration 189
7.3.2 Circular queue implementation 190
7.4 HDL templates for memory inference 194
7.4.1 Methods to incorporate memory modules 194
7.4.2 Synchronous dual-port RAM 195
7.4.3 "Simple" synchronous dual-port RAM 196
7.4.4 Synchronous single-port RAM 197
7.4.5 Synchronous ROM 198
7.4.6 BRAM-based FIFO buffer 199
7.4.7 Design considerations 200
7.5 Overview of the memory controller 200
7.6 Bibliographic notes 202
7.7 Suggested experiments 202
7.7.1 ROM-based sign-magnitude adder 202
7.7.2 ROM-based temperature conversion 202
7.7.3 FIFO with data width conversion 203
7.7.4 Standard FIFO to FWFT FIFO conversion circuit 203
7.7.5 FIFO buffer with extended status 203
7.7.6 Stack 203
PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM 205
8 Overview of Embedded SoC Systems 207
8.1 Embedded SoC 207
8.1.1 Overview of embedded systems 207
8.1.2 FPGA-based SoC 208
8.1.3 IP cores 208
8.2 Development flow of the embedded SoC 209
8.2.1 Hardware-software partition 209
8.2.2 Hardware development flow 209
8.2.3 Software development flow 211
8.2.4 Physical implementation and test 211
8.2.5 Custom IP core development 211
8.3 FPro SoC platform 212
8.3.1 Motivations 212
8.3.2 Platform hardware organization 213
8.3.3 Platform software organization 215
8.3.4 Modified development flow 216
8.4 Adaptation on the Digilent Nexys 4 DDR board 216
8.5 Portability 218
8.5.1 Processor module and bridge 218
8.5.2 MMIO subsystem 219
8.5.3 Video subsystem 219
8.6 Organization 220
8.7 Bibliographic notes 220
9 Bare Metal System Software Development 223
9.1 Bare metal system development overview 223
9.1.1 Desktop-like system versus bare metal system 223
9.1.2 Basic embedded program architecture 224
9.2 Memory-mapped I/O 225
9.2.1 Overview 225
9.2.2 Memory alignment 226
9.2.3 I/O register map 226
9.2.4 I/O address space of the FPro system 226
9.3 Direct I/O register access 227
9.3.1 Review of C pointer 227
9.3.2 C pointer for I/O register 228
9.4 Robust I/O register access 229
9.4.1 chu_io_map.h and chu_io_map.vhd 229
9.4.2 inttypes.h 230
9.4.3 chu_io_rw.h 231
9.5 Techniques for low-level I/O operations 233
9.5.1 Bit manipulation 233
9.5.2 Packing and unpacking 234
9.6 Device drivers 235
9.6.1 Overview 235
9.6.2 GPO and GPI drivers 235
9.6.3 Timer driver 237
9.6.4 UART driver 239
9.7 FPro utility routines and directory structure 240
9.7.1 Minimal hardware requirements 240
9.7.2 Utility routines 240
9.7.3 Directory structure 243
9.8 Test program 243
9.8.1 IP core verification routine 243
9.8.2 Programming with limited memory 244
9.8.3 Test function integration 244
9.8.4 Test program for the vanilla FPro system 245
9.8.5 Implementation 246
9.9 Bibliographic notes 247
9.10 Suggested experiments 247
9.10.1 Chasing LEDs 247
9.10.2 Collision LEDs 247
9.10.3 Pulse width modulation 248
9.10.4 System time display 248
10 FPro Bus Protocol and MMIO Slot Specification 249
10.1 FPro bus 249
10.1.1 Overview of the bus 249
10.1.2 SoC interconnect 250
10.1.3 FPro bus protocol specification 251
10.2 Interface with the bus 252
10.2.1 Introduction 252
10.2.2 Write interface and decoding 253
10.2.3 Read interface and multiplexing 255
10.2.4 FIFO buffer as an I/O register 256
10.2.5 Timing consideration 257
10.3 MMIO I/O core 258
10.3.1 MMIO slot interface specification 258
10.3.2 Basic MMIO I/O core construction 260
10.3.3 GPO and GPI cores 261
10.4 Timer core development 263
10.4.1 Custom logic 263
10.4.2 Register map 263
10.4.3 Wrapping circuit for the slot interface 264
10.5 MMIO controller 265
10.5.1 chu_io_map.vhd file 265
10.5.2 HDL code 267
10.5.3 Vanilla MMIO subsystem 268
10.6 MCS I/O bus and bridge 271
10.6.1 Overview of Xilinx MicroBlaze MCS 271
10.6.2 MicroBlaze MCS I/O bus 271
10.6.3 MCS-to-FPro bridge 273
10.7 Vanilla FPro system construction 274
10.8 Bibliographic notes 276
10.9 Suggested experiments 277
10.9.1 FPro bus with a byte-lane enable signal 277
10.9.2 Seven-segment control with a GPO core 277
10.9.3 GPIO core 277
10.9.4 Blinking-LED core 278
10.9.5 Timer core with a programmable period 278
10.9.6 Timer core with a run-once mode 278
11 UART Core 281
11.1 Introduction 281
11.1.1 Overview of serial communication 281
11.1.2 Overview of UART 282
11.1.3 Oversampling procedure 282
11.2 UART Construction 283
11.2.1 Conceptual design 283
11.2.2 Baud rate generator 284
11.2.3 UART receiver 285
11.2.4 UART transmitter 288
11.2.5 Top-level HDL codes 290
11.3 UART core development 291
11.3.1 Register map 292
11.3.2 Wrapping circuit for the slot interface 292
11.4 UART driver 294
11.4.1 Class definition 294
11.4.2 Basic methods 295
11.4.3 ASCII code 296
11.4.4 Display methods 297
11.4.5 Test 300
11.5 Additional project ideas 300
11.5.1 Original serial port 300
11.5.2 Emulated serial port 301
11.5.3 Direct connection 301
11.5.4 USB-to-UART adaptor 302
11.5.5 Wireless adaptor 302
11.6 Bibliographic notes 303
11.7 Suggested experiments 304
11.7.1 UART-controlled chasing LEDs 304
11.7.2 Alternative read configuration 304
11.7.3 UART controller with a parity bit 304
11.7.4 UART core with an error status 304
11.7.5 Configurable UART core 305
11.7.6 UART core with automatic baud rate detection 305
11.7.7 UART core with enhanced automatic baud rate detection 306
11.7.8 UART core with an automatic baud rate and a parity detection circuit 306
PART III EMBEDDED SOC II: BASIC I/O CORES 307
12 Xilinx XADC Core 309
12.1 Overview of XADC 309
12.1.1 Block diagram 309
12.1.2 Configuration 310
12.2 XADC core development 311
12.2.1 XADC instantiation 311
12.2.2 Basic wrapping circuit design 312
12.2.3 Register map 313
12.2.4 HDL code 314
12.3 XADC core device driver 316
12.3.1 Class definition 316
12.3.2 Class implementation 317
12.3.3 Testing for the XADC core 318
12.4 Sampler FPro system 319
12.4.1 Testing procedure of an FPro core 319
12.4.2 System configuration 319
12.4.3 Hardware derivation 320
12.4.4 Software verification program 328
12.5 Additional project ideas 329
12.6 Bibliographic notes 330
12.7 Suggested experiments 330
12.7.1 Real-time voltage display 330
12.7.2 Potentiometer-controlled chasing LEDs 330
12.7.3 Potentiometer-controlled LED dimmer 331
12.7.4 Enhanced wrapping circuit I 331
12.7.5 Enhanced wrapping circuit II 331
13 Pulse Width Modulation Core 333
13.1 Introduction 333
13.1.1 PWM as analog output 333
13.1.2 Main characteristics 334
13.2 PWM design 334
13.2.1 Basic design 334
13.2.2 Enhanced design 336
13.3 PWM core development 337
13.3.1 Register map 337
13.3.2 Wrapped PWM circuit 338
13.4 PWM driver 340
13.4.1 Class definition 340
13.4.2 Class implementation 340
13.5 Testing 341
13.6 Project ideas 342
13.7 Suggested experiments 343
13.7.1 Police dash light 343
13.7.2 Rainbow night light 343
13.7.3 Enhanced PWM core: part I 343
13.7.4 Enhanced PWM core: part II 344
13.7.5 Enhanced GPIO core 344
13.7.6 Servo motor driver 344
14 Debouncing Core and LED-Mux Core 345
14.1 Debouncing core 345
14.1.1 Multi-bit debouncing circuit 345
14.1.2 Register map and the slot wrapping circuit 348
14.1.3 Driver 349
14.1.4 Test 350
14.2 LED-Mux core 351
14.2.1 Eight-digit seven-segment LED display multiplexing circuit 351
14.2.2 Register map and the slot wrapping circuit 352
14.2.3 Driver 354
14.2.4 Test 356
14.3 Project ideas 357
14.4 Suggested experiments 358
14.4.1 Area comparison of two debouncing circuits 358
14.4.2 Enhanced debouncing core: part I 359
14.4.3 Enhanced debouncing core: part II 359
14.4.4 Rotating square pattern revisited 359
14.4.5 Heartbeat pattern revisited 359
14.4.6 Stopwatch 359
14.4.7 Enhanced LED-mux core 359
15 SPI Core 361
15.1 Overview 361
15.1.1 Conceptual architecture 362
15.1.2 Multiple device configuration 362
15.1.3 Basic timing 364
15.1.4 Operation modes 365
15.1.5 Undefined aspects 366
15.2 SPI controller 367
15.2.1 Basic design 367
15.2.2 FSMD construction 368
15.2.3 HDL implementation 368
15.3 SPI core development 372
15.3.1 Register map 372
15.3.2 Wrapping circuit for the slot interface 372
15.4 SPI Driver 374
15.4.1 Class definition 374
15.4.2 Class implementation 375
15.5 Test 376
15.5.1 ADXL362 accelerometer 377
15.5.2 Test program 378
15.6 Project ideas 379
15.6.1 SD card 379
15.6.2 TFT LCD module 379
15.7 Bibliographic notes 380
15.8 Suggested experiments 380
15.8.1 Inclination sensing 380
15.8.2 "Tapping" detection 381
15.8.3 ADXL362 C++ class 381
15.8.4 Enhanced SPI controller: part I 381
15.8.5 Enhanced SPI controller: part II 381
15.8.6 Automatic-read ADXL362 wrapper: part I 382
15.8.7 Automatic-read ADXL362 wrapper: part II 382
15.8.8 Flash memory access 382
15.8.9 SPI slave controller: part I 382
15.8.10 SPI slave controller: part II 383
16 I2C Core 385
16.1 Overview 385
16.1.1 Electrical characteristics 386
16.1.2 Basic bus protocol 386
16.1.3 Basic timing 387
16.1.4 Additional features 388
16.2 I2C controller 389
16.2.1 Basic design 389
16.2.2 Conceptual FSMD construction 389
16.2.3 Output control logic 392
16.2.4 I2C bus clock generation 392
16.2.5 HDL implementation 393
16.3 I2C core development 398
16.3.1 Register map 398
16.3.2 Wrapping circuit for the slot interface 398
16.4 I2C driver 400
16.4.1 Class definition 400
16.4.2 Class implementation 400
16.5 Test 403
16.5.1 ADT7420 temperature sensor 403
16.5.2 Test program 404
16.6 Project idea 405
16.7 Bibliographic notes 405
16.8 Suggested experiments 406
16.8.1 Thermometer 406
16.8.2 ADT7420 C++ class 406
16.8.3 Enhanced I2C core 406
16.8.4 Automatic-read ADT7420 wrapper 406
16.8.5 I2C slave controller: part I 407
16.8.6 I2C slave controller: part II 407
17 PS2 Core 409
17.1 Introduction 409
17.1.1 PS2-device-to-host communication protocol and timing 410
17.1.2 Host-to-PS2-device communication protocol and timing 410
17.2 PS2 controller 411
17.2.1 Conceptual design 411
17.2.2 PS2 receiving subsystem 411
17.2.3 PS2 transmitting subsystem 415
17.2.4 Complete PS2 system 420
17.3 PS2 core development 421
17.3.1 Register map 421
17.3.2 Wrapping circuit for the slot interface 421
17.4 PS2 driver 423
17.4.1 Class definition 423
17.4.2 Lower layer methods 423
17.4.3 PS2 initialization routine 424
17.4.4 Keyboard routine 426
17.4.5 Mouse routine 429
17.5 Test 431
17.6 Bibliographic notes 432
17.7 Suggested experiments 432
17.7.1 PS2 receiving subsystem with watchdog timer 432
17.7.2 Keyboard-controlled LED ashing circuit 432
17.7.3 Enhanced keyboard driver routine I 433
17.7.4 Enhanced keyboard driver routine II 433
17.7.5 Remote-mode mouse driver 433
17.7.6 Scroll-wheel mouse driver 433
18 Sound I: DDFS Core 435
18.1 Introduction 435
18.2 Design and implementation 436
18.2.1 Direct synthesis of a digital waveform 436
18.2.2 Direct synthesis of an unmodulated analog waveform 437
18.2.3 Direct synthesis of a modulated analog waveform 438
18.3 Fixed-point arithmetic 439
18.4 DDFS Construction 440
18.5 DAC (digital-to-analog converter) 443
18.5.1 Conceptual design 443
18.5.2 HDL implementation 444
18.6 DDFS core development 445
18.6.1 Register map 445
18.6.2 Wrapping circuit for the slot interface 446
18.7 DDFS driver 448
18.7.1 Class definition 448
18.7.2 Class implementation 448
18.8 Testing 450
18.9 Bibliographic notes 451
18.10 Suggested experiments 451
18.10.1 Quadrature phase carrier generation 452
18.10.2 Reduced-size phase-to-amplitude lookup table 452
18.10.3 Additive harmonic synthesis 452
18.10.4 Simple function generator 452
18.10.5 Arbitrary waveform generator 452
18.10.6 Sample-based synthesis 453
19 Sound II: ADSR Core 455
19.1 Introduction 455
19.2 ADSR envelope generator 456
19.2.1 Conceptual FSMD design 457
19.2.2 ASMD chart 457
19.2.3 HDL implementation 459
19.3 ADSR core development 461
19.3.1 Register map 461
19.3.2 Wrapped ADSR circuit 462
19.4 ADSR driver 464
19.4.1 Class definition 464
19.4.2 Configuration methods 465
19.4.3 calc_note_freq() method 467
19.4.4 play_note() method 468
19.5 Testing 469
19.6 Project idea 470
19.7 Bibliographic notes 471
19.8 Suggested experiments 471
19.8.1 RTTTL music player 471
19.8.2 ADSR envelope testing 471
19.8.3 Pushbutton piano 471
19.8.4 Keyboard piano 471
19.8.5 Keyboard recorder 471
19.8.6 Real-time mode ADSR generator 472
19.8.7 Real-time mode button piano 472
19.8.8 Merged DDFS and ADSR core 472
19.8.9 ADSR core with an automatic play FIFO buffer 472
19.8.10 ADSR core for frequency modulation 472
PART IV EMBEDDED SOC III: VIDEO CORES 473
20 Introduction to the Video System 475
20.1 Introduction to a video display 475
20.1.1 Conceptual video display 475
20.1.2 VGA interface 476
20.2 Stream interface 477
20.2.1 Random-access interface versus stream interface 477
20.2.2 Flow control of the stream interface 477
20.3 VGA synchronization 479
20.3.1 Basic operation of a CRT monitor 479
20.3.2 Horizontal synchronization 480
20.3.3 Vertical synchronization 482
20.3.4 Pixel clock rate 483
20.3.5 VGA synchronization circuit 484
20.4 Bar test-pattern generator 488
20.5 Color-to-grayscale conversion circuit 490
20.6 Demo video system 491
20.7 Advanced video standards 493
20.8 Bibliographic notes 494
20.9 Suggested experiments 494
20.9.1 Horizontal bar test-pattern generator 494
20.9.2 Color channel selection circuit 494
20.9.3 Enhanced color-to-grayscale conversion circuit 494
20.9.4 Square test-pattern generator: part I 494
20.9.5 Square test-pattern generator: part II 495
20.9.6 Square test-pattern generator: part III 495
20.9.7 Square test-pattern generator: part IV 495
21 FPro Video Subsystem 497
21.1 Organization of the video subsystem 497
21.1.1 Overview 497
21.1.2 Video controller 499
21.1.3 HDL of the video controller 500
21.2 FPro video IP core 501
21.2.1 Basic functionality 501
21.2.2 Blending operation 502
21.2.3 Core architecture 504
21.2.4 Alternative core partition 506
21.3 Example video cores 506
21.3.1 Bar test-pattern generator core 506
21.3.2 Color-to-grayscale conversion core 509
21.3.3 "Dummy" core 510
21.4 FPro video synchronization core 511
21.4.1 Line buffer 512
21.4.2 Enhanced video synchronization circuit 515
21.4.3 HDL code 518
21.5 Daisy video subsystem 519
21.5.1 Subsystem overview 519
21.5.2 Interface to the video synchronization core 520
21.5.3 HDL code 521
21.5.4 Timing and performance considerations 525
21.6 Vanilla daisy FPro system 526
21.6.1 Clock management core 526
21.6.2 Updated chu_io_map VHDL package 527
21.6.3 HDL code 527
21.7 Video driver and testing program 530
21.7.1 Updated chu_io_map.h and chu_io_rw.h files 530
21.7.2 GPV core driver 531
21.7.3 Testing program 531
21.8 Bibliographic notes 533
21.9 Suggested experiments 533
21.9.1 Color channel selection core 533
21.9.2 Enhanced color-to-grayscale conversion core 533
21.9.3 Square test-pattern generator core 534
21.9.4 Alpha blending circuit 534
21.9.5 "Highlight" core 534
21.9.6 SVGA synchronization core 534
21.9.7 Configurable video synchronization core 535
21.9.8 Pipelined video subsystem 535
22 Sprite Core 537
22.1 Introduction 537
22.2 Basic design 538
22.2.1 Sprite RAM 538
22.2.2 In-region comparison circuit 539
22.3 Mouse pointer core 540
22.3.1 Pointer sprite RAM 540
22.3.2 Pixel generation circuit 541
22.3.3 Top-level design 543
22.4 "Ghost" character core 545
22.4.1 Multiple images and animation 545
22.4.2 Overview of the palette scheme 546
22.4.3 Ghost sprite RAM and the palette circuit 546
22.4.4 Animation timing circuit 548
22.4.5 Pixel generation circuit 548
22.4.6 Top-level design 551
22.5 Sprite core driver and testing program 553
22.5.1 Sprite core driver 553
22.5.2 Testing program 554
22.6 Bibliographic notes 556
22.7 Suggested experiments 556
22.7.1 Mouse pointer control with a PS2 core 556
22.7.2 Emulated ghost core 556
22.7.3 Palette circuit for the mouse pointer sprite 556
22.7.4 Sprite scaling circuit 556
22.7.5 Portrait mode display 556
22.7.6 Multiple object generation 557
22.7.7 Animation speed control 557
22.7.8 Imitated blinking LED: part I 557
22.7.9 Imitated blinking LED: part II 558
22.7.10 Imitated blinking LED: part III 558
23 On-Screen-Display Core 559
23.1 Introduction to tile graphics 559
23.2 Basic OSD design 561
23.2.1 Text-mode display 561
23.2.2 Font ROM 562
23.2.3 Tile RAM 562
23.2.4 Basic organization 563
23.3 OSD core 564
23.3.1 Font ROM 564
23.3.2 Pixel generation circuit 565
23.3.3 Top-level design 568
23.4 OSD core driver and testing program 570
23.4.1 OSD core driver 570
23.4.2 Testing program 571
23.5 Bibliographic notes 572
23.6 Suggested experiments 572
23.6.1 Rotating banner 572
23.6.2 Text console 572
23.6.3 Underline for the cursor 573
23.6.4 Portrait-mode display 573
23.6.5 Font scaling circuit: part I 573
23.6.6 Font scaling circuit: part II 573
23.6.7 Extended font 573
23.6.8 Tile-based ghost core 574
24 VGA Frame Buffer Core 575
24.1 Overview 575
24.2 Frame buffer core 576
24.2.1 FPGA memory consideration 576
24.2.2 Video memory module 576
24.2.3 Address translation 578
24.2.4 Pixel generation circuit 578
24.3 Register map 580
24.3.1 Top-level HDL code 581
24.4 Driver and the testing program 582
24.4.1 Frame buffer core driver 582
24.4.2 Geometrical modeling 583
24.4.3 Testing program 585
24.5 Project ideas 585
24.6 Bibliographic notes 586
24.7 Suggested experiments 587
24.7.1 Virtual prototyping board panel 587
24.7.2 Virtual analog wall clock 587
24.7.3 Geometrical model functions 587
24.7.4 Simulated "Etch A Sketch" toy 587
24.7.5 Frame buffer core with 3-bit color depth 587
24.7.6 Frame buffer core with 1-bit color depth 588
24.7.7 QVGA frame buffer core 588
24.7.8 Line drawing hardware accelerator 588
24.7.9 Bidirectional frame buffer access: part I 588
24.7.10 Bidirectional frame buffer access: part II 588
PART V EPILOGUE 591
25 What's Next 593
References 597
Appendix A: Tutorials 601
A.1 Overview of the Xilinx Vivado IDE 601
A.2 Short tutorial on Vivado hardware development 605
A.2.1 Create a design project 606
A.2.2 Add or create Xilinx IP core instances 607
A.2.3 Add or create HDL design files 607
A.2.4 Add a constraint file 608
A.2.5 Perform synthesis, implementation, and bitstream generation 609
A.2.6 Program an FPGA device 609
A.3 Short tutorial on Vivado simulation 610
A.3.1 Add or create an HDL testbench 612
A.3.2 Perform initial simulation 613
A.3.3 Customize waveform display 613
A.4 Tutorial on IP instantiation 614
A.4.1 Dual-clock FIFO core via HDL templates 615
A.4.2 IP catalog utility 615
A.4.3 Generate a MicroBlaze MCS component 616
A.4.4 XADC IP core 617
A.4.5 Clock management IP core 619
A.5 Short tutorial on FPro system development 620
A.5.1 Derive FPro system hardware 621
A.5.2 Export hardware configuration 621
A.5.3 Derive software 622
A.5.4 Embed elf file and regenerate bitstream 626
A.5.5 Set up a terminal emulator program 626
A.5.6 Program an FPGA device 627
A.6 Bibliographic notes 627
Topic Index 629
EULA 632

Produkt-Details

• Erscheint lt. Verlag: 12.10.2017
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: circuit design with VHDL • circuit simulation with VHDL • Circuit Theory & Design • Computer Science • Electrical & Electronics Engineering • Elektrotechnik u. Elektronik • Embedded Systems • embedded systems design • embedded systems on fpga design • field programmable gate array • FPGA • FPGA design analysis • FPGA programming • FPGA Prototyping • FPGA prototyping by VHDL examples • hardware design with VHDL • Informatik • <p>HDL • MicroBlaze • register transfer level • RTL • RTL Design • Schaltkreise - Theorie u. Entwurf • SoC • SOC design • Software engineering • Software-Engineering • software-hardware co-design • software-hardware co-design with MicroBlaze</p> • synthesis of HDL with Xilinx • System on chip • System on Chip Design • timing analysis • VHDL • VHDL design • VHDL examples • VHDL synthesis • XDAC • Xilinx • Xilinx analog-to-digital converter
• ISBN-10: 1-119-28275-6 / 1119282756
• ISBN-13: 978-1-119-28275-4 / 9781119282754