Routing Algorithms in Networks-on-Chip
Springer-Verlag New York Inc.
978-1-4939-5511-4 (ISBN)
Part I Performance Improvement.- Basic Concepts on On-Chip Networks.- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs.- Run-Time Deadlock Detection.- The Abacus Turn Model.- Learning-based Routing Algorithms for on-Chip Networks.- Part II Multicast Communication.- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip.- Path-based Multicast Routing for 2D and 3D Mesh Networks.- Part III Fault Tolerance and Reliability.- Fault-Tolerant Routing Algorithms in Networks-on-Chip.- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip.
Erscheinungsdatum | 02.09.2016 |
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Zusatzinfo | 97 Illustrations, color; 122 Illustrations, black and white; XIV, 410 p. 219 illus., 97 illus. in color. |
Verlagsort | New York |
Sprache | englisch |
Maße | 155 x 235 mm |
Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
Technik ► Elektrotechnik / Energietechnik | |
ISBN-10 | 1-4939-5511-X / 149395511X |
ISBN-13 | 978-1-4939-5511-4 / 9781493955114 |
Zustand | Neuware |
Informationen gemäß Produktsicherheitsverordnung (GPSR) | |
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