Alpha AXP Architecture Reference Manual (eBook)

Richard L. Sites, Richard T. Witek (Autoren)

eBook Download: PDF

2014 | 2. Auflage
858 Seiten
Elsevier Science (Verlag)
978-1-4831-8403-6 (ISBN)

Infos

Alpha AXP Architecture Reference Manual, Second Edition describes the required behavior of all Alpha implementations, as seen by the machine-language programmer. This book discusses Alpha single-board computers, which have been introduced to cover the high-end embedded controller market. Organized into five parts, this edition begins with an overview of the instruction-set architecture. This text then describes the supporting PALcode routines for three operating systems. Other parts consider a particular console implementation that is specific to platforms that support the OpenVMS AXP or DEC OSF/1 operating systems. This book discusses as well the specific operating system PALcode architecture. The final part provides a discussion of console issues for Windows NT with its PALcode description. This book is a valuable resource for machine-language programmers.

Inhalt

Front Cover 1
Alpha Axp Architecture Reference Manual 4
Copyright Page 5
Table of Contents 6
FOREWORD 8
Preface to the First Edition 12
Preface to the Second Edition 16
Part 1: Common Architecture (I) 18
Chapter 1. Introduction (I) 28
1.1 The Alpha AXP Approach to RISC Architecture 28
1.2 Data Format Overview 30
1.3 Instruction Format Overview 31
1.4 Instruction Overview 32
1.5 Instruction Set Characteristics 33
1.6 Terminology and Conventions 34
Chapter 2. Basic Architecture (I) 38
2.1 Addressing 38
2.2 Data Types 38
2.3 Big-endian Addressing Support 51
Chapter 3. Instruction Formats (I) 54
3.1 Alpha AXP Registers 54
3.2 Notation 56
3.3 Instruction Formats 62
Chapter 4. Instruction Descriptions (I) 68
4.1 Instruction Set Overview 68
4.2 Memory Integer Load/Store Instructions 71
4.3 Control Instructions 83
4.4 Integer Arithmetic Instructions 90
4.5 Logical and Shift Instructions 104
4.6 Byte-Manipulation Instructions 110
4.7 Floating-Point Instructions 124
4.8 Memory Format Floating-Point Instructions 145
4.9 Branch Format Floating-Point Instructions 154
4.10 Floating-Point Operate Format Instructions 157
4.11 Miscellaneous Instructions 186
4.12 VAX Compatibility Instructions 195
Chapter 5. System Architecture and Programming Implications 198
5.1 Introduction 198
5.2 Physical Address Space Characteristics 198
5.3 Translation Buffers and Virtual Caches 201
5.4 Caches and Write Buffers 201
5.5 Data Sharing 202
5.6 Read/Write Ordering 206
5.7 Arithmetic Traps 223
Chapter 6. Common PALcode Architecture (I) 226
6.1 PALcode 226
6.2 PALcode Instructions and Functions 226
6.3 PALcode Environment 227
6.4 Special Functions Required for PALcode 227
6.5 PALcode Effects on System Code 228
6.6 PALcode Replacement 228
6.7 Required PALcode Instructions 229
Chapter 7. Console Subsystem Overview (I) 236
Chapter 8. Input/Output Overview (I) 238
Specific Operating System PALcode Architecture (II) 240
Part 2: OpenVMS AXP Software (ll–A) 242
Chapter 1. Introduction to OpenVMS AXP (II–A) 252
1.1 Register Usage 252
Chapter 2. OpenVMS AXP PALcode Instruction Descriptions (ll–A) 254
2.1 Unprivileged General OpenVMS AXP PALcode Instructions 256
2.2 OpenVMS AXP Queue Data Types 274
2.3 Unprivileged OpenVMS AXP Queue PALcode Instructions 283
2.4 Unprivileged VAX Compatibility PALcode Instructions 329
2.5 Unprivileged PALcode Thread Instructions 334
2.6 Privileged PALcode Instructions 337
Chapter 3. OpenVMS AXP Memory Management (II–A) 350
3.1 Introduction 350
3.2 Virtual Address Space 350
3.3 Physical Address Space 352
3.4 Memory Management Control 352
3.5 Page Table Entries 352
3.6 Memory Protection 356
3.7 Address Translation 357
3.8 Translation Buffer 360
3.9 Address Space Numbers 361
3.10 Memory Management Faults 361
Chapter 4. OpenVMS AXP Process Structure (II–A) 364
4.1 Process Definition 364
4.2 Hardware Privileged Process Context 365
4.3 Asynchronous System Traps (AST) 367
4.4 Process Context Switching 367
Chapter 5. OpenVMS AXP Internal Processor Registers (ll–A) 370
5.1 Internal Processor Registers 370
5.1 Internal Processor Registers 370
5.2 Stack Pointer Internal Processor Registers 370
5.3 IPR Summary 371
Chapter 6. OpenVMS AXP Exceptions, Interrupts, and Machine Checks (ll–A) 402
6.1 Introduction 402
6.2 Processor State and Exception/Interrupt/Machine Check Stack Frame 407
6.3 Exceptions 410
6.4 Interrupts 420
6.5 Machine Checks 425
6.6 System Control Block 428
6.7 PALcode Support 434
Part 3: DEC OSF/1 Software (II–B) 442
Chapter 1. Introduction to DEC OSF/1 (II–B) 448
1.1 Programming Model 449
Chapter 2. DEC OSF/1 PALcode Instruction Descriptions (II–B) 454
2.1 Unprivileged PALcode Instructions 454
2.2 Privileged DEC OSF/1 PALcode Instructions 461
Chapter 3. DEC OSF/1 Memory Management (II–B) 488
3.1 Virtual Address Spaces 488
3.2 Physical Address Space 490
3.3 Memory Management Control 490
3.4 Page Table Entries 490
3.5 Memory Protection 493
3.6 Address Translation for Seg0 and Seg1 494
3.7 Translation Buffer 495
3.8 Address Space Numbers 496
3.9 Memory-Management Faults 497
Chapter 4. DEC OSF/1 Process Structure (II–B) 498
4.1 Process Definition 498
4.2 Process Control Block (PCB) 498
Chapter 5. DEC OSF/1 Exceptions and Interrupts (II–B) 502
5.1 Introduction 502
5.2 Processor Status 503
5.3 Stack Frames 504
5.4 System Entry Addresses 505
5.5 PALcode Support 510
Part 4: Windows NT AXP Software (ll–C) 512
Chapter 1. Introduction to Windows NT AXP Software (II–C) 518
1.1 Overview of System Components 519
1.2 Calling Standard Register Usage 520
1.3 Code Flow Conventions 521
Chapter 2. Processor, Process, and Thread Structures and Registers (II–C) 522
2.1 Processor Status 522
2.2 Internal Processor Register Summary 523
2.3 Internal Processor Registers 524
2.4 Processor Data Areas 527
2.5 Caches and Cache Coherency 528
2.6 Stacks 528
2.7 Processes and Threads 529
Chapter 3. Memory Management (II–C) 532
3.1 Virtual Address Space 532
3.2 I/O Space Address Extension 532
3.3 Canonical Virtual Address Format 533
3.4 Page Table Entries 533
3.5 Translation Buffer Management 536
3.6 Implications of Recursive TB Mapping 537
Chapter 4. Exceptions, Interrupts, and Machine Checks (ll–C) 540
4.1 Exceptions 540
4.2 Interrupts 551
4.3 Machine Checks 556
Chapter 5. Windows NT AXP PALcode Instruction Descriptions (ll–C) 560
5.1 Privileged PALcode Instructions 561
5.2 Unprivileged PALcode Instructions 599
5.3 Debug PALcode and Free PALcode 608
Chapter 6. Initialization and Firmware Transitions (II–C) 610
6.1 Initialization 610
6.2 Firmware Interfaces 612
Part 5: Console Interface Architecture (III) 616
Chapter 1. Console Subsystem Overview (III) 622
1.1 Console Implementations 623
1.2 Console Implementation Registry 624
1.3 Console Presentation Layer 624
1.4 Messages 625
1.5 Security 625
1.6 Internationalization 625
Chapter 2. Console Interface to Operating System Software (III) 628
2.1 Hardware Restart Parameter Block (HWRPB) 628
2.2 Environment Variables 651
2.3 Console Callback Routines 656
2.4 Interprocessor Console Communications 698
Chapter 3. System Bootstrapping (III) 702
3.1 Processor States and Modes 702
3.2 System Initialization 705
3.3 PALcode Loading and Switching 706
3.4 System Bootstrapping 710
3.5 System Restarts 728
3.6 Bootstrap Loading and Image Media Format 737
3.7 BB_WATCH 745
3.8 Implementation Considerations 747
Appendixes 750
Appendix A: Software Considerations 756
A.1 Hardware-Software Compact 756
A.2 Instruction-Stream Considerations 757
A.3 Data-Stream Considerations 761
A.4 Code Sequences 766
A.5 Timing Considerations: Atomic Sequences 772
Appendix B: IEEE Floating-Point Conformance 774
B.1 Alpha AXP Choices for IEEE Options 774
B.2 Alpha AXP Hardware Support of Software Exception Handlers 775
B.3 Mapping to IEEE Standard 778
Appendix C: Instruction Summary 786
C.1 Common Architecture Instruction Summary 786
C.2 IEEE Floating-Point Instructions 791
C.3 VAX Floating-Point Instructions 793
C.4 Opcode Summary 794
C.5 Common Architecture Opcodes in Numerical Order 796
C.6 OpenVMS AXP PALcode instruction Summary 800
C.7 DEC OSF/1 PALcode Instruction Summary 802
C.8 Windows NT AXP Instruction Summary 803
C.9 PALcode Opcodes in Numerical Order 805
C.10 Required PALcode Function Codes 808
C.11 Opcodes Reserved to PALcode 808
C.12 Opcodes Reserved to Digital 808
C.13 Unused Function Code Behavior 808
C.14 ASCII Character Set 810
Appendix D: Waivers and Implementation-Dependent Functionality 812
D.1 Waivers 812
D.2 Implementation-Specific Functionality 813
Index 830

Produkt-Details

• Erscheint lt. Verlag: 16.5.2014
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• ISBN-10: 1-4831-8403-X / 148318403X
• ISBN-13: 978-1-4831-8403-6 / 9781483184036