Alpha Architecture Reference Manual (eBook)

Alpha Architecture Committee (Autor)

eBook Download: PDF

2014 | 1. Auflage
600 Seiten
Elsevier Science (Verlag)
978-1-4832-9433-9 (ISBN)

Infos

This is the authoritative reference on Digital Equipment Corporation's new 64-bit RISC Alpha architecture. Written by the designers of the internal Digital specifications, this book contains complete descriptions of the common architecture required for all implementations and the interfaces required to support the OSF/1 and OpenVMS operating systems.

Inhalt

Front Cover 1
Alpha Architecture Reference Manual 4
Copyright Page 5
Table of Contents 6
Foreword 8
Preface 10
Part I: Common Architecture 16
Chapter 1. Introduction 26
1.1 The Alpha Approach to RISC Architecture 26
1.2 Data Format Overview 28
1.3 Instruction Format Overview 29
1.4 Instruction Overview 30
1.5 Instruction Set Characteristics 31
1.6 Terminology and Conventions 32
Chapter 2. Basic Architecture 36
2.1 Addressing 36
2.2 Data Types 36
Chapter 3. Instruction Formats 50
3.1 Alpha Registers 50
3.2 Notation 51
3.3 Instruction Formats 57
Chapter 4. Instruction Descriptions 64
4.1 Instruction Set Overview 64
4.2 Memory Integer Load/Store Instructions 67
4.3 Control Instructions 78
4.4 Integer Arithmetic Instructions 85
4.5 Logical and Shift Instructions 99
4.6 Byte-Manipulation Instructions 105
4.7 Floating-Point Instructions 119
4.8 Memory Format Floating-Point Instructions 131
4.9 Branch Format Floating-Point Instructions 140
4.10 Floating-Point Operate Format Instructions 143
4.11 Miscellaneous Instructions 176
4.12 VAX Compatibility Instructions 184
Chapter 5. System Architecture and Programming Implications 186
5.1 Introduction 186
5.2 Physical Memory Behavior 186
5.3 Translation Buffers and Virtual Caches 188
5.4 Caches and Write Buffers 189
5.5 Data Sharing 190
5.6 Read/Write Ordering 194
Chapter 6. Common PALcode Architecture 208
6.1 PALcode 208
6.2 PALcode Instructions and Functions 208
6.3 PALcode Environment 209
6.4 Special Functions Required for PALcode 209
6.5 PALcode Effects on System Code 210
6.6 PALcode Replacement 210
6.7 Required PALcode Instructions 211
Chapter 7. Console Subsystem Overview 216
Chapter 8. Input/Output 218
8.1 Introduction 218
8.2 Local I/O Space Access 219
8.3 Remote I/O Space Access 219
8.4 Direct Memory Accesss (DMA) 227
8.5 Interrupts 229
8.6 I/O Bus-Specific Mailbox Usage 229
Part II: OpenVMS Alpha Software 232
Chapter 1. Introduction to OpenVMS Alpha 242
1.1 Register Usage 242
Chapter 2. OpenVMS PALcode Instruction Descriptions 244
2.1 Unprivileged General OpenVMS PALcode Instructions 246
2.2 OpenVMS Alpha Queue Data Types 264
2.3 Unprivileged OpenVMS Queue PALcode Instructions 273
2.4 Unprivileged VAX Compatibility PALcode Instructions 319
2.5 Unprivileged PALcode Thread Instructions 324
2.6 Privileged PALcode Instructions 327
Chapter 3. OpenVMS Memory Management 336
3.1 Introduction 336
3.2 Virtual Address Space 336
3.3 Physical Address Space 338
3.4 Memory Management Control 338
3.5 Page Table Entries 338
3.6 Memory Protection 342
3.7 Address Translation 343
3.8 Translation Buffer 346
3.9 Address Space Numbers 347
3.10 Memory Management Faults 348
Chapter 4. OpenVMS Process Structure 350
4.1 Process Definition 4-14.2 Hardware Privileged Process Context 350
4.2 Hardware Privileged Process Context 351
4.3 Asynchronous System Traps (AST) 352
4.4 Process Context Switching 353
Chapter 5. OpenVMS Internal Processor Registers 354
5.1 Internal Processor Registers 354
5.2 Stack Pointer Internal Processor Registers 354
5.3 IPR Summary 355
Chapter 6. OpenVMS Exceptions, Interrupts, and Machine Checks 386
6.1 Introduction 386
6.2 Processor State and Exception/Interrupt/Machine Check Stack Frame 390
6.3 Exceptions 393
6.4 Interrupts 402
6.5 Machine Checks 407
6.6 System Control Block 410
6.7 PALcode Support 416
Part III: DEC OSF/1 Alpha Software 424
Chapter 1. Introduction to DEC OSF/1 Alpha 430
1.1 Programming Model 431
Chapter 2. OSF/1 PALcode Instruction Descriptions 434
2.1 Unprivileged PALcode Instructions 434
2.2 Privileged OSF/1 PALcode Instructions 441
Chapter 3. OSF/1 Memory Management 460
3.1 Virtual Address Spaces 460
3.2 Physical Address Space 462
3.3 Memory Management Control 462
3.4 Page Table Entries 462
3.5 Memory Protection 464
3.6 Address Translation for SegO and Segl 465
3.7 Translation Buffer 467
3.8 Address Space Numbers 467
3.9 Memory-Management Faults 468
Chapter 4. OSF/1 Process Structure 470
4.1 Process Definition 470
4.2 Process Control Block (PCB) 470
Chapter 5. OSF/1 Exceptions and Interrupts 472
5.1 Introduction 472
5.2 Processor Status 473
5.3 Stack Frames 474
5.4 System Entry Addresses 474
5.5 PALcode Support 479
Appendixes 480
A Software Considerations 486
A.1 Hardware-Software Compact 486
A.2 Instruction-Stream Considerations 487
A. 3 Data-Stream Considerations 491
A.4 Code Sequences 496
A.5 Timing Considerations: Atomic Sequences 502
B IEEE Floating-Point Conformance 504
B.1 Alpha Choices for IEEE Options 504
B.2 Alpha Hardware Support of Software Exception Handlers 505
B.3 Mapping to IEEE Standard 506
C Instruction Encodings 514
C.1 Memory Format Instructions 514
C.2 Branch Format Instructions 515
C.3 Operate Format Instructions 515
C.4 Floating-Point Operate Format 516
C.5 Opcode Summary 519
C.6 OpenVMS PALcode Format Instructions 521
C.7 Unprivileged OSF/1 PALcode Function Codes 522
C.8 Privileged OSF/1 PALcode function codes 522
C.9 Required PALcode Function Codes 523
C.10 Opcodes Reserved to PALcode 523
C.11 Opcodes Reserved to Digital 523
Index 524

Produkt-Details

• Erscheint lt. Verlag: 28.6.2014
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Betriebssysteme / Server
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• ISBN-10: 1-4832-9433-1 / 1483294331
• ISBN-13: 978-1-4832-9433-9 / 9781483294339