Computer Engineering (eBook)

A DEC View of Hardware Systems Design

C. Gordon Bell, John E. McNamara, J. Craig Mudge (Autoren)

eBook Download: PDF

2014 | 1. Auflage
608 Seiten
Elsevier Science (Verlag)
978-1-4832-2110-6 (ISBN)

Infos

Computer Engineering: A DEC View of Hardware Systems Design focuses on the principles, progress, and concepts in the design of hardware systems. The selection first elaborates on the seven views of computer systems, technology progress in logic and memories, and packaging and manufacturing. Concerns cover power supplies, DEC computer packaging generations, general packaging, semiconductor logic technology, memory technology, measuring (and creating) technology progress, structural levels of a computer system, and packaging levels-of -integration. The manuscript then examines transistor circuitry in the Lincoln TX-2, digital modules, PDP-1 and other 18-bit computers, PDP-8 and other 12-bit computers, and structural levels of the PDP-8. The text takes a look at cache memories for PDP-11 family computers, buses, DEC LSI-11, and design decisions for the PDP-11/60 mid-range minicomputer. Topics include reliability and maintainability, price/performance balance, advances in memory technology, synchronization of data transfers, error control strategies, PDP-11/45, PDP-11/20, and cache organization. The selection is a fine reference for practicing computer designers, users, programmers, designers of peripherals and memories, and students of computer engineering and computer science.

Inhalt

Front Cover 1
Computer Engineering: A Dec View of Hardware Systems Design 2
Copyright Page 3
Table of Contents 20
FOREWORD 6
PREFACE 8
ACKNOWLEDGEMENTS 16
Chapter 1. Seven Views of Computer Systems 24
VIEW 1 : STRUCTURAL LEVELS OF A COMPUTER SYSTEM 25
VIEW 2: LEVY'S LEVELS-OF-INTERPRETERS 26
VIEW 3: PACKAGING LEVELS-OF-INTEGRATION 29
VIEW 4: A MARKETPLACE VIEW OF COMPUTER CLASSES 32
VIEW 5: AN APPLICATIONS/ FUNCTIONAL VIEW OF COMPUTER CLASSES 38
VIEW 6: THE PRACTICE OF DESIGN 41
VIEW 7: THE BLAAUW CHARACTERIZATION OF COMPUTER DESIGN 47
Chapter 2. Technology Progress in Logic and Memories 50
SEMICONDUCTOR LOGIC TECHNOLOGY 51
MEMORY TECHNOLOGY 69
MEASURING (AND CREATING) TECHNOLOGY PROGRESS 76
SUMMARY 85
Chapter 3. Packaging and Manufacturing 86
GENERAL PACKAGING 86
THE DEC COMPUTER PACKAGING GENERATIONS 96
POWER SUPPLIES 103
HEAT 106
AN OVERVIEW OF MANUFACTURING 107
ACKNOWLEDGEMENTS 114
PART 1: IN THE BEGINNING 116
In the Beginning 118
Chapter 4. Transistor Circuitry in the Lincoln TX-2 120
CIRCUIT CONFIGURATIONS 120
FLIP-FLOP 122
MARGINAL CHECKING 123
PACKAGING 124
CONCLUSION 125
ACKNOWLEDGEMENTS 125
Chapter 5. Digital Modules, The Basis for Computers 126
ACKNOWLEDGEMENTS 141
PART 2: BEGINNING OF THE MINICOMPUTER 142
Beginning of the Minicomputer 144
ACKNOWLEDGEMENTS 145
Chapter 6. The PDP-1 and Other 18-Bit Computers 146
THE PDP-1 146
THE PDP-7 170
THE PDP-9 176
THE PDP-15 179
DUAL CENTRAL PROCESSOR PDP-15 185
PDP-15/76 185
THE SERIES AND ITS EVOLUTION 187
ACKNOWLEDGEMENTS 197
Chapter 7. The PDP-8 and Other 12-Bit Computers 198
THE LINC 198
THE PDP-5 201
THE PDP-8 202
THE PDP-8/E, PDP-8/M, AND PDP-8/A 205
TECHNOLOGY, PRICE, AND PERFORMANCE OF THE 12-BIT FAMILY 216
SPECIAL DEVICES BASED ON THE PDP-8 223
The PDP-14 226
ACKNOWLEDGEMENTS 231
Chapter 8. Structural Levels of the PDP-8 232
ABSTRACT REPRESENTATIONS 233
THE PMS LEVEL 233
PROGRAMMING LEVEL (ISP) 238
THE INTERRUPT SCHEME 241
REGISTER TRANSFER LEVEL 241
LOGIC DESIGN LEVEL (REGISTERS AND DATA OPERATIONS) 245
LOGIC DESIGN LEVEL (PC CONTROL PC(K) SEQUENTIAL STATE MACHINE NETWORK) 245
CIRCUIT LEVEL 247
PART 3: THE PDP-11 FAMILY 252
The PDP-11 Family 254
INTRODUCTION TO THE PDP-11 254
CONCEPTUAL BASIS FOR THE PDP-11 MODELS 255
IMPLEMENTATIONS OF THE PDP-11 256
EVALUATION OF THE PDP-11 261
VIRTUAL ADDRESS EXTENSION OF THE PDP-11 262
Chapter 9. A New Architecture for Minicomputers -The DEC PDP-11 264
INTRODUCTION 264
DESIGN CONSTRAINTS 265
PDP-11 STRUCTURE AT THE PMS LEVEL 267
THE INSTRUCTION SET PROCESSOR (ISP) LEVEL-ARCHITECTURE 272
LOGICAL DESIGN OF S(UNIBUS) AND Pc 280
CONCLUSIONS 281
ACKNOWLEDGEMENTS 282
APPENDIX. DEC PDP-11 INSTRUCTION SET PROCESSOR DESCRIPTION (IN ISPL) 282
Chapter 10. Cache Memories for PDP-11 Family Computers 286
INTRODUCTION 286
CACHE MEMORY 286
CACHE ORGANIZATION 287
CACHE MEMORY SIMULATION 288
CACHE SIMULATION RESULTS 289
CONCLUSIONS 290
Chapter 11. Buses, The Skeleton of Computer Structures 292
INTRODUCTION 292
FUNCTIONS OF BUSES IN COMPUTER SYSTEMS: A FIVE-FUNCTION MODEL 294
EVOLUTION OF THE HIGH PERFORMANCE PDP-11 SYSTEMS 300
PDP-11/20 300
PDP-11/45 300
PDP-11/70 301
VAX-11/780 302
ARBITRATION METHODS 303
SYNCHRONIZATION OF DATA TRANSFERS 309
ERROR CONTROL STRATEGIES 317
ACKNOWLEDGEMENTS 321
APPENDIX: A GLOSSARY OF TERMS 321
ANNOTATED BIBLIOGRAPHY 321
Chapter 12. A Minicomputer-Compatible Microcomputer System: The DEC LSI-11 324
INTRODUCTION 324
THE COMPUTER DESIGNER'S VIEW 325
THE USER'S OUTLOOK 331
SUMMARY 336
ACKNOWLEDGEMENTS 336
Chapter 13. PDP-11/60 Design Decisions for the Mid-Range Minicomputer 338
INTRODUCTION 338
DESIGN STYLES 338
ADVANCES IN MEMORY TECHNOLOGY 339
PRICE/PERFORMANCE BALANCE 341
FREQUENCY-DRIVEN DESIGN 344
INTEGRAL FLOATING-POINT ARITHMETIC UNIT 344
CABINET-LEVEL INTEGRATION 345
USER MICROPROGRAMMING OPTION 345
RELIABILITY AND MAINTAINABILITY 347
MTBF 347
MTTR 347
SUMMARY 349
Chapter 14. Impact of Implementation Design Tradeoffs on Performance: The PDP-11, A Case Study 350
INTRODUCTION 350
IMPLEMENTATION OF MEDIUM PERFORMANCE PDP-11s 351
IMPLEMENTATION OF A MINIMAL COST PDP-11 367
IMPLEMENTATION OF A HIGH PERFORMANCE PDP-11 370
MEASURING THE EFFECT OF DESIGN TRADEOFFS ON PERFORMANCE 372
SUMMARY AND USE OF THE METHODOLOGIES 377
APPENDIX A: INSTRUCTION TIME COMPONENT FREQUENCIES 379
LSI-11 NOTES 383
PDP-11/04 NOTES 383
PDP-11/10 NOTES 384
PDP-11/20 NOTES 384
PDP-11/34 NOTES 384
PDP-11/40 NOTES 385
PDP-11/45 NOTES 385
PDP-11/60 NOTES 386
Chapter 15. Turning Cousins into Sisters: An Example of Software Smoothing of Hardware Differences 388
INTRODUCTION 388
FORTRAN MACHINE - PHASE 1 391
FORTRAN MACHINE - PHASE 2 395
REAL MICROCODE AND THE FORTRAN MACHINE 400
ACKNOWLEDGEMENTS 401
Chapter 16. The Evolution of the PDP-11 402
EVALUATION AGAINST THE ORIGINAL GOALS 404
EVOLUTION OF THE INSTRUCTION SET PROCESSOR 406
THE EVOLUTION OF THE PMS (MODULAR) STRUCTURE 410
MULTIPROCESSORS 414
TECHNOLOGY: COMPONENTS OF THE DESIGN 426
VAX-11 428
ACKNOWLEDGEMENTS 431
Chapter 17. VAX-11/780: A Virtual Address Extension to the DEC PDP-11 Family 432
INTRODUCTION 432
VAX-11 Overview 433
VAX-11 NATIVE ARCHITECTURE 434
I/O 446
VAX-11/780 IMPLEMENTATION VAX-11/780 446
CPU 446
SBI 447
ACKNOWLEDGEMENTS 449
APPENDIX- VAX-11 INSTRUCTION SET 449
PART 4: EVOLUTION OF COMPUTER BUILDING BLOCKS 452
Evolution of Computer Building Blocks 454
REGISTER TRANSFER MODULES (RTMs) 454
BIT-SLICES (FRACTIONAL REGISTER TRANSFER LEVEL MODULES) AS BUILDING BLOCKS 458
COMPUTER MODULES 459
CONCLUSIONS 463
Chapter 18. The Description and Use of Register Transfer Modules (RTMs) 464
INTRODUCTION 464
MODULE DESIGN CONSIDERATIONS 465
THE RTM SYSTEM 465
DESIGN WITH RTMs 468
CONCLUSIONS 471
ACKNOWLEDGEMENT 471
Chapter 19. Using LSI Processor Bit-Slices to Build a PDP-11 - A Case Study in Microcomputer Design 472
INTRODUCTION 472
ORGANIZATION OF THE CMU-11 473
EVALUATION OF CMU-11 DESIGN 477
SOME PITFALLS FOUND IN IMPLEMENTING THE PDP-11 WITH THE 3000 BIT-SLICES 481
ADDITIONAL COMMENTS ON THE CMU-11 DESIGN 483
COMPUTER-AIDED DESIGN TOOLS 483
CONCLUDING COMMENTS 484
Chapter 20. Multi-Microprocessors: An Overview and Working Example 486
INTRODUCTION 486
OVERVIEW OF MULTIPLE PROCESSOR STRUCTURES 488
THE ARCHITECTURE OF Cm 492
MEASUREMENT AND EVALUATION OF Cm 500
CONCLUDING REMARKS 505
APPENDIX: DESCRIPTION OF THE BENCHMARK PROGRAMS 505
ACKNOWLEDGEMENTS 507
PART 5: THE PDP-10 FAMILY 508
The PDP-10 Family 510
Chapter 21. The Evolution of the DECsystem-10 512
INTRODUCTION 512
HISTORICAL SETTING 512
OVERALL GOALS, CONSTRAINTS, AND BASIC DESIGN DECISIONS 515
THE INSTRUCTION SET PROCESSOR 515
PMS STRUCTURE 522
OPERATING SYSTEM 528
HARDWARE IMPLEMENTATION 535
CONCLUSIONS 541
ACKNOWLEDGEMENTS 541
APPENDIX 1: An ISPS Primer for the Instruction Set Processor Notation 542
INSTRUCTION SET PROCESSOR DESCRIPTIONS 542
PARTITIONING THE DESCRIPTION 545
EFFECTIVE ADDRESS 547
INSTRUCTION INTERPRETATION 549
OTHER FEATURES OF ISPS 555
APPENDIX 2: The PMS Notation 560
PMS PRIMITIVES 560
APPENDIX 3: Performance 564
PMS (RESOURCES) PERFORMANCE PARAMETERS 565
THE MULTIPROCESSOR CASE 567
ISP (ARCHITECTURE) PARAMETERS 569
ACTUAL (COMPOUND PMS/ISP) PERFORMANCE MEASURE 572
TYPICAL INSTRUCTIONS 573
STANDARD BENCHMARKS 573
EXACT USE CHARACTERIZATION 575
BIBLIOGRAPHY 576
INDEX 586

Produkt-Details

• Erscheint lt. Verlag: 12.5.2014
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Technik ► Bauwesen
• Themenwelt: Technik ► Maschinenbau
• ISBN-10: 1-4832-2110-5 / 1483221105
• ISBN-13: 978-1-4832-2110-6 / 9781483221106