Microprocessor Architectures and Systems (eBook)

RISC, CISC and DSP

Steve Heath (Autor)

eBook Download: PDF

2014 | 1. Auflage
302 Seiten
Elsevier Science (Verlag)
978-1-4832-7824-7 (ISBN)

Infos

Microprocessor Architectures and Systems: RISC, CISC, and DSP focuses on the developments of Motorola's CISC, RISC, and DSP processors and the advancements of the design, functions, and architecture of microprocessors. The publication first ponders on complex instruction set computers and 32-bit CISC processors. Discussions focus on MC68881 and MC68882 floating point coprocessors, debugging support, MC68020 32-bit performance standard, bus interfaces, MC68010 SUPERVISOR resource, and high-level language support. The manuscript then covers the RISC challenge, digital signal processing, and memory management and caches. Topics include implementing memory systems, multitasking and user/supervisor conflicts, partitioning the system, cache size and organization, DSP56000 family, MC88100 programming model, M88000 family, and the 80/20 rule. The text examines the selection of a microprocessor architecture, changing design cycle, semiconductor technology, multiprocessing, and real-time software, interrupts, and exceptions. Concerns include locating associated tasks, MC88100 interrupt service routines, single- and multiple-threaded operating systems, and the MC68300 family. The publication is a valuable reference for computer engineers and researchers interested in microprocessor architectures and systems.

Senior Staff Engineer, European Strategy and Technology Development, Motorola Semiconductors, Steve Heath has written 15 books on topics covering Apple and IBM PCs, processor architectures, UNIX and Windows NT operating systems.

Inhalt

Front Cover 1
Microprocessor Architectures and Systems: RISC, CISC and DSP 4
Copyright Page 5
Dedication 6
Table of Contents 8
Preface 12
Acknowledgements 14
Chapter 1. Complex instruction setcomputers 16
8-bit microprocessors: the precursors of CISC 16
8-bit microprocessor register models 18
Restrictions 19
Addressing memory 21
System integrity 22
Requirements for a new processor architecture 23
Software compatibility 24
Enter the MC68000 26
Complex instructions, microcode and nanocode 27
The MC68000 hardware 29
M68000 asynchronous bus 31
M6800 synchronous bus 34
Interrupts 34
Error recovery and control signals 35
Bus arbitration 37
Typical system 38
The register set 38
The USER/SUPERVISOR concept 40
Exceptions and the vector table 41
Addressing modes 43
Instruction set 44
High-level language support 49
Start of a revolution 51
The MC68010 virtual memory processor 51
MC68010 SUPERVISOR resource 55
Other improvements 56
The MC68008 57
The story continues 58
Chapter 2. 32-bit CISC processors 59
Enter HCMOS technology 59
Architectural challenges 60
The MC68020 32-bit performance standard 62
The programmer's model 64
Bus interfaces 67
Dynamic bus sizing 68
On-chip instruction cache 70
Debugging support 74
Coprocessor interface 75
MC68881 and MC68882 floating point coprocessors 78
The MC68851 paged memory management unit (PMMU) 79
The MC68030 - the first commercial 50 MHz processor 81
Chapter 3. The RISC challenge 87
The 80/20 rule 87
The initial RISC research 88
The M88000 family 91
The MC88100 programming model 98
The MC88100 instruction set 100
MC88100 external functions 103
MC88200 cache MMU 106
The MBUS protocol 109
Chapter 4. Digital signal processing 113
Processor requirements 116
The DSP56000 family 117
The programming model 125
Chapter 5. Memory, memory managementand caches 134
Achieving processor throughput 134
Partitioning the system 136
Shadow RAM 137
DRAM v. SRAM 138
Memory management 142
Multitasking and user/supervisor conflicts 149
Cache size and organization 152
Cache coherency 158
Implementing memory systems 166
Conclusions 167
Chapter 6. Real-time software, interrupts and exceptions 169
What is real-time software? 169
Responding to an interrupt 170
Interrupting the processor 170
Servicing the interrupt 170
Locating associated tasks 171
Context switches 172
Improving performance 173
Interrupting an MC88100 173
MC88100 interrupt service routines 174
Interrupting the DSP56000 178
The M68300 family 184
Conclusions 189
Chapter 7. Multiprocessing 190
SISD - Single instruction, single data 191
SIMD - Single instruction, multiple data 191
MIMD - Multiple instruction, multiple data 192
MISD - Multiple instruction, single data 192
Constructing a MIMD architecture 193
Fault-tolerant systems 199
Single- and multiple-threaded operating systems 202
Chapter 8. Application ideas 204
1 MC68020 and MC68030 design techniques for highreliability applications 204
2 Upgrading 8-bit systems 213
3 Transparent update techniques for digital filters usingthe DSP56000 217
4 Motor and servo control 220
Chapter 9. Semiconductor technology 228
Silicon technology 228
CMOS and bipolar technology 230
Fabrication technology 232
Packaging 233
Processor technology 236
Memory technology 236
Science fiction or not? 237
Chapter 10. The changing design cycle 239
The shortening design cycle 239
The double-edged sword of technology 241
Make v. Buy 241
Simulation v. emulation 247
Chapter 11. The next generations 252
Enter the MC68040 252
The MC68300 family 261
Improving the instruction set 265
DSP96000 - combining integration and performance 271
Chapter 12. Selecting a microprocessor architecture 274
Meeting performance needs 274
Software support 275
Development support 276
Standards 278
Built-in obsolescence 280
Market changes 280
Considering all the options 281
Appendix A: Benchmarking 282
Appendix B: Binary compatibilitystandards 288
Index 295

Produkt-Details

• Erscheint lt. Verlag: 12.5.2014
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Betriebssysteme / Server
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Mathematik / Informatik ► Mathematik
• ISBN-10: 1-4832-7824-7 / 1483278247
• ISBN-13: 978-1-4832-7824-7 / 9781483278247