Digital Logic Design (eBook)

B. Holdsworth (Autor)

eBook Download: PDF

2014 | 2. Auflage
462 Seiten
Elsevier Science (Verlag)
978-1-4831-4222-7 (ISBN)

Infos

Digital Logic Design, Second Edition provides a basic understanding of digital logic design with emphasis on the two alternative methods of design available to the digital engineer. This book describes the digital design techniques, which have become increasingly important. Organized into 14 chapters, this edition begins with an overview of the essential laws of Boolean algebra, K-map plotting techniques, as well as the simplification of Boolean functions. This text then presents the properties and develops the characteristic equations of a number of various types of flip-flop. Other chapters consider the design of synchronous and asynchronous counters using either discrete flip-flops or shift registers. This book discusses as well the design and implementation of event driven logic circuits using the NAND sequential equation. The final chapter deals with simple coding techniques and the principles of error detection and correction. This book is a valuable resource for undergraduate students, digital engineers, and scientists.

Inhalt

Front Cover 1
Digital Logic Design 4
Copyright Page 5
Table of Contents 10
Dedication 
3 
Preface to the Second Edition 6
Preface to the First Edition 7
Chapter 1. 
16 
1.1 Introduction 16
1.2 The logic of a switch 17
1.3 The AND function 17
1.4 The OR function 19
1.5 The inversion function 20
1.7 The idempotency theorem 22
1.8 The theorems of union and intersection 23
1.9 The redundancy or absorption theorem 24
1.10 The determination of the complementary function 25
1.11 Theorems on commutation, association and distribution 27
1.12 The consensus theorem 28
Problems 29
Chapter 2. Karnaugh maps and function simplification 31
2.1 Introduction 31
2.2 Product and sum terms 31
2.3 Canonical forms 33
2.4 Boolean functions of two variables 33
2.5 The Karnaugh map 35
2.6 Plotting Boolean functions on a Karnaugh map 37
2.7 Simplification of Boolean functions 40
2.8 The inverse function 42
2.9 'Don't care' terms 43
2.10 The plotting and simplification of P-of-S expressions 45
2.11 The Quine-McCluskey tabular simplification method 47
2.12 Properties of prime implicant tables 52
2.13 Cyclic prime implicant tables 53
2.14 Semi-cyclic prime implicant tables 56
2.15 Simplification of functions containing 'can't happen' term 57
2.16 The decimal approach to Quine-McCluskey 57
Problems 61
Chapter 3. 
64 
3.1 Introduction 64
3.2 The NAND function 64
3.3 The implementation of AND and OR functions using NAND gates 66
3.4 The implementation of S-of-P expressions using NAND gates 67
3.5 The NOR function 70
3.6 The implementation of OR and AND functions using NOR gates 71
3.7 The implementation of P-of-S expressions using NOR gates 72
3.8 The implementation of S-of-P expressions using NOR gates 72
3.9 Gate expansion 74
3.10 Miscellaneous gates 75
3.11 The tri-state gate 78
3.12 The exclusive-OR gate 78
Problems 83
Chapter 4. 
85 
4.1 Introduction 85
4.2 The half-adder 86
4.3 The full adder 87
4.4 The full subtracter 89
4.5 Comparators 91
4.6 Parity generation and checking 92
4.7 Code conversion 97
4.8 Binary to Gray code converter 99
4.9 Interrupt sorters 102
Problems 104
Chapter 5. 
106 
5.1 Introduction 106
5.2 The T flip-flop 106
5.3 The SR flip-flop 110
5.4 The JK flip-flop 114
5.5 The D flip-flop 119
5.6 The edge-triggered flip-flop 121
5.7 The latching action of a flip-flop 123
Problems 125
Chapter 6. 
128 
6.1 Introduction 128
6.2 Scale-of-two up-counter 128
6.3 Scale-of-four up-counter 130
6.4 Scaleof-eight up-counter 130
6.5 Scale-of 2N up-counter 131
6.6 Series and parallel connection of counters 132
6.7 Synchronous down-counters 133
6.8 Scale-of five up-counter 133
6.9 Decade binary up-counter 137
6.10 Decade binary down-counter 140
6.11 Decade Gray code 'up' counter 140
6.12 Scale-of-16 up/down counter 145
6.13 Asynchronous binary counters 146
6.14 Scale-often asynchronous up-counter 149
6.15 Asynchronous resettable counters 150
6.16 Integrated-circuit counters 151
6.17 Cascading of IC counter chips 154
Problems 155
Chapter 7. Shift register counters and generators 158
7.1 Introduction 158
7.2 The four-bit shift register with parallel loading 159
7.3 The four-bit shift-left, shift-right register 159
7.4 The use of shift registers as counters 160
7.5 The universal state diagram for shift registers 162
7.6 The design of a decade counter 164
7.7 Shift register sequence generators 167
7.8 The ring counter 170
7.9 The twisted ring or Johnson counter 174
7.10 Shift registers with exclusive-OR feedback 177
Problems 183
Chapter 8. 
185 
8.1 Introduction 185
8.2 Analysis of a clocked sequential circuit 185
8.3 The design procedure for clocked sequential circuits 190
8.4 The design of a sequence generator 198
8.5 Moore and Mealy state machines 201
8.6 Pulsed synchronous circuits 205
8.7 State reduction 208
8.8 State assignment 213
Problems 218
Chapter 9. 
223 
9.1 Introduction 223
9.2 The museum problem 223
9.3 Races and cycles 227
9.4 Race-free assignment for a three-state machine 230
9.5 The pump problem 231
9.6 Race-free assignment for a four-state machine 234
9.7 A sequence detector 237
Problems 243
Chapter 10. 
248 
10.1 Introduction 248
10.2 Data selector or multiplexer 249
10.3 The multiplexer as a logic function generator 250
10.4 Decoders and demultiplexers 259
10.5 Decoder applications 260
10.6 Read-only memories (ROMs) 265
10.7 Addressing techniques for ROMs 267
10.8 Design of sequential circuits using ROMs 269
10.9 Programmable logic arrays (PLAs) 274
10.10 Design of sequential circuits using PLA s 277
Problems 280
Chapter 11. 
285 
11.1 Introduction 285
11.2 The four-bit parallel adder 285
11.3 The carry look-ahead adder 286
11.4 Complement arithmetic 290
11.5 The 2's complement 291
11.6 The 1's complement 291
11.7 Representation of binary numbers in a digital machine 292
11.8 Addition and subtraction using 2's complement arithmetic 293
11.9 Addition and subtraction using 1's complement arithmetic 294
11.10 Overflow 295
11.11 Serial addition and subtraction 297
11.12 Decimal arithmetic with MSI adders 298
11.13 The use of complement arithmetic for decimal operations 301
11.14 Adder/subtractor for decimal arithmetic 304
11.15 Arithmetic/logic unit 306
11.16 Design of an arithmetic/logic unit 307
11.17 Combinational binary multipliers 311
11.18 ROM implemented binary multipliers 314
11.19 The shift and add multiplier 317
11.20 Binary division 321
Problems 325
Chapter 12. 
329 
12.1 Introduction 329
12.2 Gate delays 329
12.3 The generation of spikes 330
12.4 The production of static hazards in combinational networks 332
12.5 The elimination of static hazards 334
12.6 Design of hazard-free combinational network« 337
12.7 Detection of hazards in an existing network 340
12.8 Hazard-free asynchronous circuit design 342
12.9 Dynamic hazards 345
12.10 Essential hazards 347
Problems 349
Chapter 13. Fault diagnosis in combinational circuits 351
13.1 Introduction 351
13.2 Fault detection and location 352
13.3 A fault test for a 2-input AND gate 354
13.4 The fault detection table 355
13.5 The fault location table 361
13.6 Adaptive testing 362
13.7 Path sensitisation 365
13.8 Path sensitisation applied to combinational networks 367
13.9 Path sensitisation in networks with fanout 370
13.10 Two-level circuit fault detection in AND/OR circuit 374
13.11 Two-level circuit fault detection in OR/AND circuits 378
13.12 Tabulation method of fault diagnosis for two-level circuits 382
13.13 Fault detection in multi-level circuits 385
13.14 Boolean difference 388
13.15 The chain tuie 392
Problems 396
Chapter 14. 
400 
14.1 Introduction 400
14.2 Definition of a code 401
14.3 Information content of the decimal and hexadecimal numbersystems 401
14.4 Coding theory terminology 402
14.5 The conditions for error detection 403
14.6 The Boolean Circle and the correction domain 405
14.7 The transmission equation 406
14.8 The undetected error rate 407
14.9 Linear block codes 409
14.10 Backward error correction (BEC) 410
14.11 Matrix representation of linear block codes 414
14.12 Decoding the received word 418
14.13 Forward error correction 420
Problems 423
Answers to problems 425
Bibliography 456
Index 458

Produkt-Details

• Erscheint lt. Verlag: 12.5.2014
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• ISBN-10: 1-4831-4222-1 / 1483142221
• ISBN-13: 978-1-4831-4222-7 / 9781483142227