Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
Springer-Verlag New York Inc.
978-1-4899-8696-2 (ISBN)
Regular vs Irregular TSV Placementfor 3D IC.- Steiner Routingfor 3D IC.- Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC.- Power Delivery Network Design for 3D IC.- 3D Clock Routing for Pre-bond Testability.- TSV-to-TSV Coupling Analysis and Optimization.- TSV Current Crowding and Power Integrity.- Modeling of Atomic Concentration at the Wire-to-TSV Interface.- Multi-Objective Archetectural Floorplanning for 3D IC.- Thermal-aware Gate-level Placement for 3D IC.- 3D IC Cooling with Micro-Fluidic Channels.- Mechanical Reliability Analysis and Optimization for 3D IC.- Impact of Mechanical Stress on Timing Variation for 3D IC.- Chip/Package Co-Analysis of Mechanical Stress for 3D IC.- 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations.- TSV Interfracial Crack Analysis and Optimization.- Ultra High Logic Designs Using Monolithic 3D Integration.- Impact of TSV Scaling on 3D IC Design Quality.- 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.
Erscheint lt. Verlag | 16.12.2014 |
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Zusatzinfo | XXVIII, 560 p. |
Verlagsort | New York |
Sprache | englisch |
Maße | 155 x 235 mm |
Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
Technik ► Elektrotechnik / Energietechnik | |
Schlagworte | design for manufacturability • design for reliability • Design for Testability • Electronic Design Automation • Embedded Systems • GDSII layouts • Integrated Circuits and Systems • Three Dimensional Integrated Circuits • Through Silicon Via • TSV |
ISBN-10 | 1-4899-8696-0 / 1489986960 |
ISBN-13 | 978-1-4899-8696-2 / 9781489986962 |
Zustand | Neuware |
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