Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs (eBook)

Brandon Noia, Krishnendu Chakrabarty (Autoren)

eBook Download: PDF

2013 | 2014
XVIII, 245 Seiten
Springer International Publishing (Verlag)
9783319023786 (ISBN)

Infos

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.


Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.

Inhalt

Introduction.- Wafer Stacking and 3D Memory Test.- Built-in Self-Test for TSVs.- Pre-Bond TSV Test Through TSV Probing.- Pre-Bond TSV Test Through TSV Probing.- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths.- Post-Bond Test Wrappers and Emerging Test Standards.- Test-Architecture Optimization and Test Scheduling.- Conclusions.

Produkt-Details

• Erscheint lt. Verlag: 19.11.2013
• Zusatzinfo: XVIII, 245 p. 133 illus., 115 illus. in color.
• Verlagsort: Cham
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: 3D Built-in Seft Test • 3D IC Test • 3D Integrated Circuit Design • 3D Memory Test • BIST for TSVs • Through-Silicon Via
• ISBN-13: 9783319023786 / 9783319023786