Systemverilog for Design and Verification Using UVM
From RTL to Synthesis
Seiten
2015
|
2015 ed.
Springer-Verlag New York Inc.
978-1-4614-1757-6 (ISBN)
Springer-Verlag New York Inc.
978-1-4614-1757-6 (ISBN)
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SystemVerilog for Design and Verification using UVM
This book is an "A-Z" guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification. Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC). To complete this book's package as a practical guide, readers are introduced to the fundamentals of static timing analysis.
This book is an "A-Z" guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification. Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC). To complete this book's package as a practical guide, readers are introduced to the fundamentals of static timing analysis.
Mark A. Aazadpour is a senior staff member at Seagate Technology, LLC.
The SystemVerilog language.- Designing with SystemVerilog.- Verification with SytemVerilog.- Building environment and the DUT.- Synthesis.- Timing analysis.
| Erscheint lt. Verlag | 1.12.2015 |
|---|---|
| Zusatzinfo | 100 black & white illustrations, biography |
| Verlagsort | New York, NY |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | ASIC • ASIC Design • ASIC Verification • SystemVerilog • SystemVerilog for Design • SystemVerilog for Verification • Universal Verification Methodology • UVM • VLSI Verification |
| ISBN-10 | 1-4614-1757-0 / 1461417570 |
| ISBN-13 | 978-1-4614-1757-6 / 9781461417576 |
| Zustand | Neuware |
| Informationen gemäß Produktsicherheitsverordnung (GPSR) | |
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