Formal Verification

An Essential Toolkit for Modern VLSI Design

Erik Seligman, Tom Schubert, M. V. Achutha Kiran Kumar (Autoren)

Buch | Softcover

424 Seiten

2023 | 2nd edition
Morgan Kaufmann (Verlag)
978-0-323-95612-3 (ISBN)

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Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes.

New sections cover advanced techniques, and a new chapter, The Road To Formal Signoff, emphasizes techniques used when replacing simulation work with Formal Verification. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity.

Erik Seligman is currently a Senior Product Engineering Architect at Cadence Design Systems, where he helps to plan and support the Jasper Formal Verification tool suite. Previously he worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. In his spare time he hosts the “Math Mutation podcast, and has served as an elected director on the Hillsboro school board. Tom Schubert is on the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis. M V Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at intel and leads the company’s Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 19 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of validation including formal verification.

Formal verification: from dreams to reality
Basic formal verification algorithms
Introduction to SystemVerilog Assertions
Formal property verification
Effective formal property verification for design exercise
Effective FPV for verification
Formal property verification apps for specific problems
Formal equivalence verification
Formal verification’s greatest bloopers: the danger of false positives
Dealing with complexity
Formal signoff on real projects
Your new FV-aware lifestyle

Erscheinungsdatum	10.07.2023
Verlagsort	London
Sprache	englisch
Maße	191 x 235 mm
Gewicht	880 g
Themenwelt	Kunst / Musik / Theater ► Design / Innenarchitektur / Mode
	Mathematik / Informatik ► Informatik
	Technik ► Elektrotechnik / Energietechnik
ISBN-10	0-323-95612-2 / 0323956122
ISBN-13	978-0-323-95612-3 / 9780323956123
Zustand	Neuware