On-Chip Communication Architectures (eBook)

System on Chip Interconnect

Nikil Dutt, Sudeep Pasricha (Autoren)

eBook Download: PDF

2010 | 1. Auflage
544 Seiten
Elsevier Science (Verlag)
978-0-08-055828-8 (ISBN)

Infos

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

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Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. On-Chip Communication Architecures is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. - A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends- Detailed analysis of all popular standards for on-chip communication architectures- Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts- Future trends that with have a significant impact on research and design of communication architectures over the next several years

Inhalt

Front Cover 1
On-Chip Communication Architectures: System on Chip Interconnect 4
Copyright Page 5
Contents 6
Preface 10
About the Authors 14
Acknowledgments 16
List of Contributors 18
CHAPTER 1 Introduction 20
1.1. Trends in System-On-Chip Design 20
1.2. Coping with Soc Design Complexity 22
1.3. ESL Design Flow 23
1.4. On-Chip Communication Architectures: A Quick Look 25
1.5. Book Outline 31
CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures 36
2.1. Terminology 37
2.2. Characteristics of Bus-Based Communication Architectures 38
2.3. Data Transfer Modes 47
2.4. Bus Topology Types 52
2.5. Physical Implementation of Bus Wires 56
2.6. Discussion: Buses in the DSM Era 57
2.7. Summary 58
CHAPTER 3 On-Chip Communication Architecture Standards 62
3.1. Standard On-Chip Bus-Based Communication Architectures 63
3.2. Socket-Based On-Chip Bus Interface Standards 107
3.3. Discussion: Off-Chip Bus Architecture Standards 115
3.4. Summary 116
CHAPTER 4 Models for Performance Exploration 120
4.1. Static Performance Estimation Models 121
4.2. Dynamic (Simulation-Based) Performance Estimation Models 130
4.3. Hybrid Communication Architecture Performance Estimation Approaches 151
4.4. Summary 157
CHAPTER 5 Models for Power and Thermal Estimation 162
5.1. Bus Wire Power Models 164
5.2. Comprehensive Bus Architecture Power Models 172
5.3. Bus Wire Thermal Models 186
5.4. Discussion: PVT Variation-Aware Power Estimation 193
5.5. Summary 198
CHAPTER 6 Synthesis of On-Chip Communication Architectures 204
6.1. Bus Topology Synthesis 206
6.2. Bus Protocol Parameter Synthesis 215
6.3. Bus Topology and Protocol Parameter Synthesis 224
6.4. Physical Implementation Aware Synthesis 235
6.5. Memory–Communication Architecture Co-synthesis 249
6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures 259
6.7. Summary 262
CHAPTER 7 Encoding Techniques for On-Chip Communication Architectures 272
7.1. Techniques for Power Reduction 274
7.2. Techniques for Reducing Capacitive Crosstalk Delay 297
7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects 301
7.4. Techniques for Reducing Inductive Crosstalk Effects 303
7.5. Techniques for Fault Tolerance and Reliability 306
7.6. Summary 311
CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design 320
8.1. Split Bus Architectures 320
8.2. Serial Bus Architectures 328
8.3. CDMA-Based Bus Architectures 329
8.4. Asynchronous Bus Architectures 332
8.5. Dynamically Reconfigurable Bus Architectures 337
8.6. Summary 355
CHAPTER 9 On-Chip Communication Architecture Refinement and Interface Synthesis 360
9.1. On-Chip Communication Architecture Refinement 362
9.2. Interface Synthesis 365
9.3. Discussion: Interface Synthesis 380
9.4. Summary 380
CHAPTER 10 Verification and Security Issues in On-Chip Communication Architecture Design 386
10.1. Verification of On-Chip Communication Protocols 388
10.2. Compliance Verification for IP Block Integration 395
10.3. Basic Concepts of SoC Security 407
10.4. Security Support in Standard Bus Protocols 410
10.5. Communication Architecture Enhancements for Improving SoC Security 410
10.6. Summary 414
CHAPTER 11 Physical Design Trends for Interconnects 422
11.1. DSM Interconnect Design 424
11.2. Low Power, High Speed Circuit Design Techniques 427
11.3. Global Power Distribution Networks 436
11.4. Clock Distribution Networks 440
11.5. 3-D Interconnects 446
11.6. Summary and Concluding Remarks 448
CHAPTER 12 Networks-On-Chip 458
12.1. Network Topology 462
12.2. Switching Strategies 467
12.3. Routing Algorithms 470
12.4. Flow Control 473
12.5. Clocking Schemes 477
12.6. Quality of Service 478
12.7. NoC Architectures 478
12.8. NoC Status and Open Problems 483
12.9. Summary 485
CHAPTER 13 Emerging On-Chip Interconnect Technologies 492
13.1. Optical Interconnects 493
13.2. RF/Wireless Interconnects 502
13.3. CNT Interconnects 509
13.4. Summary 520
Index 528
A 528
B 529
C 530
D 531
E 532
F 533
G 533
H 533
I 534
J 534
K 534
L 534
M 535
N 535
O 536
P 536
Q 537
R 538
S 538
T 540
U 540
V 541
W 541
X 541
Z 541

Produkt-Details

• Erscheint lt. Verlag: 28.7.2010
• Sprache: englisch
• Themenwelt: Kunst / Musik / Theater ► Design / Innenarchitektur / Mode
• Themenwelt: Mathematik / Informatik ► Informatik ► Theorie / Studium
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• ISBN-10: 0-08-055828-3 / 0080558283
• ISBN-13: 978-0-08-055828-8 / 9780080558288