System-on-Chip Test Architectures (eBook)

Nanometer Design for Testability

Charles E. Stroud, Nur A. Touba, Laung-Terng Wang (Autoren)

eBook Download: PDF

2010 | 1. Auflage
896 Seiten
Elsevier Science (Verlag)
978-0-08-055680-2 (ISBN)

Infos

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost.

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era, promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

---

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. - Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. - Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. - Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. - Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. - Practical problems at the end of each chapter for students.

Inhalt

Front Cover 1
System-on-Chip Test Architectures 4
Copyright Page 5
Table of Contents 6
Preface 22
In the Classroom 28
Acknowledgments 30
Contributors 32
About the Editors 36
Chapter 1 Introduction 38
1.1 Importance of System-on-Chip Testing 39
1.1.1 Yield and Reject Rate 42
1.1.2 Reliability and System Availability 43
1.2 Basics of SOC Testing 45
1.2.1 Boundary Scan (IEEE 1149.1 Standard) 46
1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard) 48
1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687) 50
1.2.4 Core-Based Testing (IEEE 1500 Standard) 50
1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard) 54
1.3 Basics of Memory Testing 57
1.4 SOC Design Examples 61
1.4.1 BioMEMS Sensor 62
1.4.2 Network-on-Chip Processor 64
1.5 About This Book 67
1.5.1 DFT Architectures 67
1.5.2 New Fault Models and Advanced Techniques 68
1.5.3 Yield and Reliability Enhancement 69
1.5.4 Nanotechnology Testing Aspects 70
1.6 Exercises 70
Acknowledgments 73
References 73
Chapter 2 Digital Test Architectures 78
2.1 Introduction 78
2.2 Scan Design 80
2.2.1 Scan Architectures 81
2.2.1.1 Muxed-D Scan Design 81
2.2.1.2 Clocked-Scan Design 83
2.2.1.3 LSSD Scan Design 84
2.2.1.4 Enhanced-Scan Design 85
2.2.2 Low-Power Scan Architectures 87
2.2.2.1 Reduced-Voltage Low-Power Scan Design 87
2.2.2.2 Reduced-Frequency Low-Power Scan Design 87
2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design 87
2.2.2.4 Bandwidth-Matching Low-Power Scan Design 88
2.2.2.5 Hybrid Low-Power Scan Design 89
2.2.3 At-Speed Scan Architectures 89
2.3 Logic Built-In Self-Test 94
2.3.1 Logic BIST Architectures 95
2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS) 95
2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO) 96
2.3.2 Coverage-Driven Logic BIST Architectures 98
2.3.2.1 Weighted Pattern Generation 98
2.3.2.2 Test Point Insertion 99
2.3.2.3 Mixed-Mode BIST 101
2.3.2.4 Hybrid BIST 102
2.3.3 Low-Power Logic BIST Architectures 103
2.3.3.1 Low-Transition BIST Design 103
2.3.3.2 Test-Vector-Inhibiting BIST Design 104
2.3.3.3 Modified LFSR Low-Power BIST Design 104
2.3.4 At-Speed Logic BIST Architectures 105
2.3.4.1 Single-Capture 105
2.3.4.2 Skewed-Load 107
2.3.4.3 Double-Capture 110
2.3.5 Industry Practices 112
2.4 Test Compression 113
2.4.1 Circuits for Test Stimulus Compression 114
2.4.1.1 Linear-Decompression-Based Schemes 114
2.4.1.2 Broadcast-Scan-Based Schemes 118
2.4.1.3 Comparison 122
2.4.2 Circuits for Test Response Compaction 124
2.4.2.1 Space Compaction 125
2.4.2.2 Time Compaction 129
2.4.2.3 Mixed Time and Space Compaction 130
2.4.3 Low-Power Test Compression Architectures 131
2.4.4 Industry Practices 132
2.5 Random-Access Scan Design 134
2.5.1 Random-Access Scan Architectures 135
2.5.1.1 Progressive Random-Access Scan Design 137
2.5.1.2 Shift-Addressable Random-Access Scan Design 138
2.5.2 Test Compression RAS Architectures 140
2.5.3 At-Speed RAS Architectures 142
2.6 Concluding Remarks 143
2.7 Exercises 143
Acknowledgments 147
References 148
Chapter 3 Fault-Tolerant Design 160
3.1 Introduction 160
3.2 Fundamentals of Fault Tolerance 161
3.2.1 Reliability 162
3.2.2 Mean Time to Failure (MTTF) 163
3.2.3 Maintainability 164
3.2.4 Availability 164
3.3 Fundamentals of Coding Theory 166
3.3.1 Linear Block Codes 166
3.3.2 Unidirectional Codes 172
3.3.2.1 Two-Rail Codes 172
3.3.2.2 Berger Codes 173
3.3.2.3 Constant Weight Codes 173
3.3.3 Cyclic Codes 174
3.4 Fault Tolerance Schemes 179
3.4.1 Hardware Redundancy 179
3.4.1.1 Static Redundancy 179
3.4.1.2 Dynamic Redundancy 183
3.4.1.3 Hybrid Redundancy 185
3.4.2 Time Redundancy 187
3.4.2.1 Repeated Execution 187
3.4.2.2 Multiple Sampling of Outputs 188
3.4.2.3 Diverse Recomputation 189
3.4.3 Information Redundancy 190
3.4.3.1 Error Detection 190
3.4.3.2 Error Correction 197
3.5 Industry Practices 200
3.6 Concluding Remarks 202
3.7 Exercises 202
Acknowledgments 205
References 205
Chapter 4 System/Network-on-Chip Test Architectures 208
4.1 Introduction 209
4.2 System-on-Chip (SOC) Testing 212
4.2.1 Modular Testing of SOCs 212
4.2.2 Wrapper Design and Optimization 214
4.2.3 TAM Design and Optimization 216
4.2.4 Test Scheduling 218
4.2.5 Modular Testing of Mixed-Signal SOCs 222
4.2.6 Modular Testing of Hierarchical SOCs 225
4.2.7 Wafer-Sort Optimization for Core-Based SOCs 228
4.3 Network-on-Chip (NOC) Testing 229
4.3.1 NOC Architectures 229
4.3.2 Testing of Embedded Cores 231
4.3.2.1 Reuse of On-Chip Network for Testing 231
4.3.2.2 Test Scheduling 233
4.3.2.3 Test Access Methods and Test Interface 234
4.3.2.4 Efficient Reuse of Network 235
4.3.2.5 Power-Aware and Thermal-Aware Testing 239
4.3.3 Testing of On-Chip Networks 240
4.3.3.1 Testing of Interconnect Infrastructures 240
4.3.3.2 Testing of Routers 242
4.3.3.3 Testing of Network Interfaces and Integrated System Testing 245
4.4 Design and Test Practice: Case Studies 246
4.4.1 SOC Testing for PNX8550 System Chip 247
4.4.2 NOC Testing for a High-End TV System 249
4.5 Concluding Remarks 252
4.6 Exercises 253
Acknowledgments 254
References 254
Chapter 5 SIP Test Architectures 262
5.1 Introduction 263
5.1.1 SIP Definition 263
5.1.2 SIP Examples 264
5.1.3 Yield and Quality Challenges 267
5.1.4 Test Strategy 270
5.2 Bare Die Test 272
5.2.1 Mechanical Probing Techniques 272
5.2.2 Electrical Probing Techniques 274
5.2.3 Reliability Screens 277
5.3 Functional System Test 279
5.3.1 Path-Based Testing 279
5.3.2 Loopback Techniques: DFT and DSP 282
5.4 Test of Embedded Components 283
5.4.1 SIP Test Access Port 284
5.4.2 Interconnections 287
5.4.3 Digital and Memory Dies 288
5.4.4 Analog and RF Components 290
5.4.4.1 Test Equipment Issues 290
5.4.4.2 Test of Analog, Mixed-Signal, and RF Dies 291
5.4.5 MEMS 292
5.5 Concluding Remarks 294
5.6 Exercises 294
Acknowledgments 295
References 295
Chapter 6 Delay Testing 300
6.1 Introduction 300
6.2 Delay Test Application 302
6.2.1 Enhanced Scan 303
6.2.2 Muxed-D Scan 303
6.2.3 Scan Clocking 303
6.2.4 Faster-Than-At-Speed Testing 305
6.3 Delary Fault Models 306
6.3.1 Transition Fault Model 306
6.3.2 Inline-Delay Fault Model 307
6.3.3 Gate-Delay Fault Model 307
6.3.4 Path-Delay Fault Model 307
6.3.5 Defect-Based Delay Fault Models 308
6.4 Delay Test Sensitization 313
6.5 Delay Fault Simulation 314
6.5.1 Transition Fault Simulation 314
6.5.2 Gate/Line Delay Fault Simulation 314
6.5.3 Path-Delay Fault Simulation 315
6.5.4 Defect-Based Delay Fault Model Simulation 315
6.6 Delay Fault Test Generation 317
6.6.1 Transition/Inline Fault ATPG 317
6.6.2 Gate-Delay Fault ATPG 319
6.6.3 Path-Delay Fault ATPG 319
6.6.4 K Longest Paths per Gate (KLPG) ATPG 320
6.7 Pseudo-Functional Testing to Avoid Over-Testing 325
6.7.1 Computing Constraints 327
6.7.1.1 Pair-Wise Constraints 328
6.7.1.2 Multiliteral Constraints 328
6.7.2 Constrained ATPG 330
6.8 Concluding Remarks 331
6.9 Exercises 332
Acknowledgments 336
References 337
Chapter 7 Low-Power Testing 344
7.1 Introduction 344
7.2 Energy and Power Modeling 346
7.2.1 Basics of Circuit Theory 347
7.2.2 Terminology 348
7.2.3 Test-Power Modeling and Evaluation 349
7.3 Test Power Issues 350
7.3.1 Thermal Effects 351
7.3.2 Noise Phenomena 351
7.3.3 Miscellaneous Issues 352
7.4 Low-Power Scan Testing 353
7.4.1 Basics of Scan Testing 353
7.4.2 ATPG and X-Filling Techniques 355
7.4.3 Low-Power Test Vector Compaction 357
7.4.4 Shift Control Techniques 358
7.4.5 Scan Cell Ordering 359
7.4.6 Scan Architecture Modification 361
7.4.7 Scan Clock Splitting 363
7.5 Low-Power Built-In Self-Test 365
7.5.1 Basics of Logic BIST 365
7.5.2 LFSR Tuning 366
7.5.3 Low-Power Test Pattern Generators 367
7.5.4 Vector Filtering BIST 368
7.5.5 Circuit Partitioning 369
7.5.6 Power-Aware Test Scheduling 371
7.6 Low-Power Test Data Compression 372
7.6.1 Coding-Based Schemes 373
7.6.2 Linear-Decompression-Based Schemes 373
7.6.3 Broadcast-Scan-Based Schemes 374
7.7 Low-Power RAM Testing 376
7.8 Concluding Remarks 378
7.9 Exercises 379
Acknowledgments 381
References 381
Chapter 8 Coping with Physical Failures, Soft Errors, and Reliability Issues 388
8.1 Introduction 389
8.2 Signal Integrity 391
8.2.1 Basic Concept of Integrity Loss 391
8.2.2 Sources of Integrity Loss 393
8.2.2.1 Interconnects 393
8.2.2.2 Power Supply Noise 395
8.2.2.3 Process Variations 395
8.2.3 Integrity Loss Sensors/Monitors 397
8.2.3.1 Current Sensor 397
8.2.3.2 Power Supply Noise Monitor 398
8.2.3.3 Noise Detector (ND) Sensor 399
8.2.3.4 Integrity Loss Sensor (ILS) 399
8.2.3.5 Jitter Monitor 400
8.2.3.6 Process Variation Sensor 401
8.2.4 Readout Architectures 402
8.2.4.1 BIST-Based Architecture 402
8.2.4.2 Scan-Based Architecture 404
8.2.4.3 PV-Test Architecture 405
8.3 Manufacturing Defects, Process Variations, and Reliability 407
8.3.1 Fault Detection 407
8.3.1.1 Structural Tests 408
8.3.1.2 Defect-Based Tests 409
8.3.1.3 Functional Tests 415
8.3.2 Reliability Stress 416
8.3.3 Redundancy and Memory Repair 418
8.3.4 Process Sensors and Adaptive Design 419
8.3.4.1 Process Variation Sensor 420
8.3.4.2 Thermal Sensor 420
8.3.4.3 Dynamic Voltage Scaling 422
8.4 Soft Errors 423
8.4.1 Sources of Soft Errors and SER Trends 424
8.4.2 Coping with Soft Errors 427
8.4.2.1 Fault Tolerance 427
8.4.2.2 Error-Resilient Microarchitectures 431
8.4.2.3 Soft Error Mitigation 435
8.5 Defect and Error Tolerance 439
8.5.1 Defect Tolerance 441
8.5.2 Error Tolerance 442
8.6 Concluding Remarks 444
8.7 Exercises 444
Acknowledgments 446
References 446
Chapter 9 Design for Manufacturability and Yield 460
9.1 Introduction 460
9.2 Yield 463
9.3 Components of Yield 464
9.3.1 Yield Models 465
9.3.2 Yield and Repair 466
9.4 Photolithography 467
9.5 DFM and DFY 470
9.5.1 Photolithography 472
9.5.2 Critical Area 476
9.5.3 Yield Variation over Time 478
9.5.4 DFT and DFM/DFY 481
9.6 Variability 482
9.6.1 Sources of Variability 482
9.6.2 Deterministic versus Random Variability 483
9.6.3 Variability versus Defectivity 485
9.6.4 Putting It All Together 486
9.7 Metrics for DFX 486
9.7.1 The Ideal Case 487
9.7.2 Potential DFY Metrics 489
9.7.2.1 Critical Area 489
9.7.2.2 RET-Based Metrics 489
9.7.2.3 Example DRC-Based Metrics for DFM 491
9.8 Concluding Remarks 493
9.9 Exercises 494
Acknowledgments 495
References 496
Chapter 10 Design for Debug and Diagnosis 500
10.1 Introduction 500
10.1.1 What Are Debug and Diagnosis? 501
10.1.2 Where Is Diagnosis Used? 502
10.1.3 IC-Level Debug and Diagnosis 502
10.1.4 Silicon Debug versus Defect Diagnosis 503
10.1.5 Design for Debug and Diagnosis 504
10.2 Logic Design for Debug and Diagnosis (DFD) Structures 505
10.2.1 Scan 505
10.2.2 Observation-Only Scan 506
10.2.3 Observation Points with Multiplexers 508
10.2.4 Array Dump and Trace Logic Analyzer 509
10.2.5 Clock Control 510
10.2.6 Partitioning, Isolation, and De-featuring 512
10.2.7 Reconfigurable Logic 513
10.3 Probing Technologies 513
10.3.1 Mechanical Probing 514
10.3.2 Injection-Based Probing 515
10.3.2.1 E-beam Probing 515
10.3.2.2 Laser Voltage Probing 516
10.3.3 Emission-Based Probing 520
10.3.3.1 Infrared Emission Microscopy (IREM) 520
10.3.3.2 Picosecond Imaging Circuit Analysis (PICA) 522
10.3.3.3 Time Resolved Emissions (TRE) 523
10.4 Circuit Editing 524
10.4.1 Focused Ion Beam 524
10.4.2 Layout-Database-Driven Navigation System 525
10.4.3 Spare Gates and Spare Wires 526
10.5 Physical DFD Structures 527
10.5.1 Physical DFD for Pico-Probing 527
10.5.2 Physical DFD for E-Beam 528
10.5.3 Physical DFD for FIB and Probing 529
10.6 Diagnosis and Debug Process 529
10.6.1 Diagnosis Techniques and Strategies 532
10.6.2 Silicon Debug Process and Flow 533
10.6.3 Debug Techniques and Methodology 534
10.7 Concluding Remarks 535
10.8 Exercises 536
Acknowledgments 537
References 537
Chapter 11 Software-Based Self-Testing 542
11.1 Introduction 543
11.2 Software-Based Self-Testing Paradigm 544
11.2.1 Self-Test Flow 545
11.2.2 Comparison with Structural BIST 546
11.3 Processor Functional Fault Self-Testing 547
11.3.1 Processor Model 547
11.3.2 Functional-Level Fault Models 549
11.3.3 Test Generation Procedures 550
11.3.3.1 Test Generation for Register Decoding Fault 550
11.3.3.2 Test Generation for Instruction Decoding and Control Fault 551
11.3.3.3 Test Generation for Data Transfer and Storage Function 552
11.3.3.4 Test Generation for Data Manipulation Function 553
11.3.3.5 Test Generation Complexity 553
11.4 Processor Structural Fault Self-Testing 553
11.4.1 Test Flow 553
11.4.1.1 Test Preparation 553
11.4.1.2 Self-Testing 554
11.4.2 Stuck-At Fault Testing 555
11.4.2.1 Instruction-Imposed I/O Constraint Extraction 555
11.4.2.2 Constrained Component Test Generation 556
11.4.2.3 Test Program Synthesis 558
11.4.2.4 Processor Self-Testing 559
11.4.3 Test Program Synthesis Using Virtual Constraint Circuits (VCCs) 560
11.4.4 Delay Fault Testing 563
11.4.4.1 Functionally Untestable Delay Faults 563
11.4.4.2 Constraint Extraction 564
11.4.4.3 Test Program Generation 565
11.4.5 Functional Random Instruction Testing 566
11.5 Processor Self-Diagnosis 567
11.5.1 Challenges to SBST-Based Processor Diagnosis 567
11.5.2 Diagnostic Test Program Generation 568
11.6 Testing Global Interconnect 570
11.6.1 Maximum Aggressor (MA) Fault Model 570
11.6.2 Processor-Based Address and Data Bus Testing 571
11.6.2.1 Data Bus Testing 571
11.6.2.2 Address Bus Testing 572
11.6.3 Processor-Based Functional MA Testing 573
11.7 Testing Nonprogrammable Cores 573
11.7.1 Preprocessing Phase 575
11.7.2 Core Test Phase 575
11.8 Instruction-Level DFT 575
11.8.1 Instruction-Level DFT Concept 575
11.8.2 Testability Instructions 576
11.8.3 Test Optimization Instructions 578
11.9 DSP-Based Analog/Mixed-Signal Component Testing 578
11.10 Concluding Remarks 580
11.11 Exercises 581
Acknowledgments 582
References 582
Chapter 12 Field Programmable Gate Array Testing 586
12.1 Overview of FPGAs 586
12.1.1 Architecture 587
12.1.2 Configuration 591
12.1.3 The Testing Problem 593
12.2 Testing Approaches 595
12.2.1 External Testing and Built-In Self-Test 596
12.2.2 Online and Offline Testing 597
12.2.3 Application Dependent and Independent Testing 598
12.3 BIST of Programmable Resources 599
12.3.1 Logic Resources 600
12.3.1.1 Programmable Logic Blocks 604
12.3.1.2 Input/Output Cells 607
12.3.1.3 Specialized Cores 608
12.3.1.4 Diagnosis 612
12.3.2 Interconnect Resources 615
12.4 Embedded Processor-Based Testing 620
12.5 Concluding Remarks 622
12.6 Exercises 623
Acknowledgments 624
References 624
Chapter 13 MEMS Testing 628
13.1 Introduction 629
13.2 MEMS Testing Considerations 630
13.3 Test Methods and Instrumentation for MEMS 631
13.3.1 Electrical Test 632
13.3.2 Optical Test Methods 633
13.3.3 Material Property Measurements 635
13.3.4 Failure Modes and Analysis 636
13.3.5 Mechanical Test Methods 637
13.3.6 Environmental Testing 644
13.4 RF MEMS Devices 646
13.4.1 RF MEMS Switches 647
13.4.2 RF MEMS Resonators 648
13.5 Optical MEMS Devices 651
13.6 Fluidic MEMS Devices 653
13.6.1 MEMS Pressure Sensor 654
13.6.2 MEMS Humidity Sensor 655
13.7 Dynamic MEMS Devices 657
13.7.1 MEMS Microphone 657
13.7.2 MEMS Accelerometer 658
13.7.3 MEMS Gyroscope 659
13.8 Testing Digital Microfluidic Biochips 662
13.8.1 Overview of Digital Microfluidic Biochips 663
13.8.2 Fault Modeling 664
13.8.3 Test Techniques 665
13.8.4 Application to a Fabricated Biochip 668
13.9 DFT and BIST for MEMS 670
13.9.1 Overview of DFT and BIST Techniques 670
13.9.2 MEMS BIST Examples 674
13.10 Concluding Remarks 680
13.11 Exercises 681
Acknowledgments 683
References 683
Chapter 14 High-Speed I/O Interfaces 690
14.1 Introduction 691
14.2 High-Speed I/O Architectures 694
14.2.1 Global Clock I/O Architectures 694
14.2.2 Source Synchronous I/O Architectures 695
14.2.3 Embedded Clock I/O Architectures 697
14.2.3.1 Jitter Components 698
14.2.3.2 Jitter Separation 699
14.2.3.3 Jitter, Noise, and Bit-Error-Rate Interactions 703
14.3 Testing of I/O Interfaces 705
14.3.1 Testing of Global Clock I/O 706
14.3.2 Testing of Source Synchronous I/O 706
14.3.3 Testing of Embedded Clock High-Speed Serial I/O 708
14.3.3.1 Transmitter 708
14.3.3.2 Channel or Medium 710
14.3.3.3 Receiver 712
14.3.3.4 Reference Clock 714
14.3.3.5 System-Level Bit-Error-Rate Estimation 715
14.3.3.6 Tester Apparatus Considerations 715
14.4 DFT-Assisted Testing 717
14.4.1 AC Loopback Testing 718
14.4.2 High-Speed Serial-Link Loopback Testing 720
14.4.3 Testing the Equalizers 723
14.5 System-Level Interconnect Testing 727
14.5.1 Interconnect Testing with Boundary Scan 727
14.5.2 Interconnect Testing with High-Speed Boundary Scan 728
14.5.3 Interconnect Built-In Self-Test 730
14.6 Future Challenges 731
14.7 Concluding Remarks 732
14.8 Exercises 733
Acknowledgments 734
References 734
Chapter 15 Analog and Mixed-Signal Test Architectures 740
15.1 Introduction 741
15.2 Analog Functional Testing 742
15.2.1 Frequency Response Testing 742
15.2.2 Linearity Testing 744
15.2.3 Signal-to-Noise Ratio Testing 746
15.2.4 Quantization Noise 747
15.2.5 Phase Noise 749
15.2.6 Noise in Phase-Locked Loops 752
15.2.6.1 In-Band PLL Phase Noise 753
15.2.6.2 Out-Band PLL Phase Noise 755
15.2.6.3 Optimal Loop Setting 755
15.2.7 DAC Nonlinearity Testing 756
15.3 Analog and Mixed-Signal Test Architectures 757
15.4 Defect-Oriented Mixed-Signal BIST Approaches 761
15.5 FFT-Based Mixed-Signal BIST 764
15.5.1 FFT 764
15.5.2 Inverse FFT 766
15.5.3 FFT-Based BIST Architecture 766
15.5.4 FFT-Based Output Response Analysis 767
15.5.5 FFT-Based Test Pattern Generation 768
15.6 Direct Digital Synthesis BIST 770
15.6.1 DDS-Based BIST Architecture 771
15.6.2 Frequency Response Test and Measurement 773
15.6.3 Linearity Test and Measurement 775
15.6.4 SNR and Noise Figure Measurement 776
15.7 Concluding Remarks 776
15.8 Exercises 777
Acknowledgments 778
References 778
Chapter 16 RF Testing 782
16.1 Introduction 783
16.1.1 RF Basics 783
16.1.2 RF Applications 785
16.2 Key Specifications for RF Systems 787
16.2.1 Test Instrumentation 787
16.2.1.1 Spectrum Analyzer 788
16.2.1.2 Network Analyzer 789
16.2.1.3 Noise Figure Meter 790
16.2.1.4 Phase Meter 792
16.2.2 Test Flow in Industry 792
16.2.2.1 Design and Fabrication 793
16.2.2.2 Characterization Test 793
16.2.2.3 Production Test 793
16.2.3 Characterization Test and Production Test 794
16.2.3.1 Accuracy 794
16.2.3.2 Time Required for Testing 795
16.2.3.3 Cost of Testing 795
16.2.4 Circuit-Level Specifications 795
16.2.4.1 Gain 796
16.2.4.2 Harmonics and Third-Order Intercept Point (IP3) 796
16.2.4.3 1-dB Compression Point (P–1dB) 800
16.2.4.4 Total Harmonic Distortion (THD) 800
16.2.4.5 Gain Flatness 801
16.2.4.6 Noise Figure 802
16.2.4.7 Sensitivity and Dynamic Range 804
16.2.4.8 Local Oscillator Leakage 805
16.2.4.9 Phase Noise 805
16.2.4.10 Adjacent Channel Power Ratio 806
16.2.5 System-Level Specifications 807
16.2.5.1 I-Q Mismatch 807
16.2.5.2 Error Vector Magnitude 808
16.2.5.3 Modulation Error Ratio 809
16.2.5.4 Bit Error Rate 810
16.2.6 Structure of RF Systems 811
16.3 Test Hardware: Tester and DIB/PIB 813
16.4 Repeatability and Accuracy 816
16.5 Industry Practices for High-Volume Manufacturing 819
16.5.1 Test Cost Analysis 820
16.5.2 Key Trends 821
16.6 Concluding Remarks 822
16.7 Exercises 823
Acknowledgments 824
References 825
Chapter 17 Testing Aspects of Nanotechnology Trends 828
17.1 Introduction 829
17.2 Resonant Tunneling Diodes and Quantum-Dot Cellular Automata 831
17.2.1 Testing Threshold Networks with Application to RTDs 832
17.2.2 Testing Majority Networks with Application to QCA 836
17.3 Crossbar Array Architectures 844
17.3.1 Hybrid Nanoscale/CMOS Structures 847
17.3.1.1 The nanoPLA 847
17.3.1.2 Molecular CMOS (CMOL) 850
17.3.2 Built-In Self-Test 852
17.3.3 Simultaneous Configuration and Test 854
17.4 Carbon Nanotube (CNT) Field Effect Transistors 857
17.4.1 Imperfection-Immune Circuits for Misaligned CNTs 857
17.4.2 Robust Circuits for Metallic CNTs 861
17.5 Concluding Remarks 863
Acknowledgments 863
References 864
Index 870

Produkt-Details

• Erscheint lt. Verlag: 28.7.2010
• Sprache: englisch
• Themenwelt: Kunst / Musik / Theater ► Design / Innenarchitektur / Mode
• Themenwelt: Mathematik / Informatik ► Informatik
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• ISBN-10: 0-08-055680-9 / 0080556809
• ISBN-13: 978-0-08-055680-2 / 9780080556802