Co-verification of Hardware and Software for ARM SoC Design (eBook)
288 Seiten
Elsevier Science (Verlag)
978-0-08-047690-2 (ISBN)
This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.
* The only book on verification for systems-on-a-chip (SoC) on the market
* Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes
* Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs
Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.* The only book on verification for systems-on-a-chip (SoC) on the market* Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes* Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs
Cover 1
Contents 5
Foreword 13
Preface 15
Why Is This Book Important? 15
Audience 16
Prerequisite Knowledge 16
About Hardware/Software Co-Verification 16
Acknowledgments 17
About the Author 19
About Verisity 21
Chapter 1: Embedded System Verification: An Introduction 25
What’s an Embedded System? 27
Embedded Systems Are Everywhere 29
Consumer Electronics 29
Wireless 29
Medical 29
Networking 29
Security 29
Imaging 29
Storage 29
Automotive 29
Design Constraints 30
Cost 30
Memory 30
Power 31
Real-Time Response 31
Performance 31
System Size 32
Reliability 32
Time-to-Market 32
Embedded Systems Decomposition 33
Microprocessors, Chips and Boards 33
Embedded System Classifications 35
Little or No Custom Hardware Design 36
A Lot of Custom Hardware – SoB Design 36
A Lot of Custom Hardware – SoC Design 37
Embedded System Design Process 38
Requirements 39
System Architecture 39
Microprocessor Selection 39
Hardware Design 40
Software Design 40
Hardware and Software Integration 40
Verification and Validation 40
Verification: Does it Work? 41
Validation: Did We Build the Right Thing? 41
Human Interaction 42
What is this Book About? 44
Scope and Outline 46
Chapter 2: Hardware and Software Design Process 49
Three Components of SoC Verification 49
Verification Platform 50
Software Engineer’s View of the World 59
Hardware Engineer’s View of the World 61
Example 61
Software Development Tools 63
Editor 63
Source Code Revision Control 63
Compiler 64
Debugger 65
Simulator 65
Development Board 66
Integrated Development Environment (IDE) 66
Software Debugging Connections 66
JTAG 67
Stub 67
Direct Connection 68
Types of Software 68
System Initialization and HAL 68
Diagnostic Suite 69
Real-Time Operating System (RTOS) 69
Device Drivers and Application Software 69
Software Development Process 70
Hardware Development Tools 76
Editor 76
Source Code Revision Control 77
Lint Tools 78
Code Coverage 78
Debugging Tools 79
Verification Languages 79
Assertions 80
Debugging Defined 82
Memory Models 83
Microprocessor Models 85
Hardware Design Process 86
Microprocessor Review 87
Hardware and Software Interaction 88
Software Debugging Characteristics 88
Hardware Debugging Characteristics 88
Chapter 3: SoC Verification Topics for the ARM Architecture 93
ARM Background 93
ARM Architecture 94
ARM Architectures, Families, and CPU Cores 95
Thumb Instruction Set 99
Programming Model 100
Instruction Set 102
Data Transfer Instructions 102
Coprocessor Instructions 103
Exceptions and Interrupts 104
Memory Layout and Byte Order 107
ARM Bus Interface Protocols 108
ARM7TDMI Bus Protocol 109
AMBA Specification 113
Introduction to AMBA Protocols 115
AMBA ASB 115
AMBA AHB 116
AMBA APB 116
AMBA 3.0 and AXI 116
Summary of ARM CPU Bus Interfaces 117
AHB Tutorial 118
Configuration at Reset 122
Phases of AHB Transfer 123
AHB Arbitration 123
AHB Address Phase 125
AHB Data Phase 128
AHB-Lite 130
Single-Layer and Multilayer AHB 131
ARM926EJ-S Example 131
Interrupt Signals 135
Instruction and Data Caches 135
Tightly Coupled Memory (TCM) 139
ARM Summary 142
Chapter 4: Hardware/Software Co-Verification 143
History of Hardware/Software Co-Verification 143
Commercial Co-Verification Tools Appear 145
Co-Verification Defined 148
Definition 148
Benefits of Co-Verification 149
Project Schedule Savings 149
Co-Verification Enables Learning by Providing Visibility 151
Co-Verification Improves Communication 151
Co-Verification versus Co-Simulation 152
Co-Verification versus Co-Design 152
Is Co-Verification Really Necessary? 153
Co-Verification Methods 153
Native Compiling Software 154
Instruction Set Simulation 154
Hardware Stubs 155
Real-Time Operating System (RTOS) Simulator 156
Microprocessor Evaluation Board 156
Waveforms, Log Files, and Disassembly 157
A Sample of Co-Verification Methods 158
Host-Code Mode with Logic Simulation 158
Instruction Set Simulation with Logic Simulation 161
C Simulation 164
RTL Model of CPU with Software Debugging 168
Hardware Model with Logic Simulation 171
Evaluation Board with Logic Simulation 173
In-Circuit Emulation 174
FPGA Prototype 177
Co-Verification Metrics 178
Performance 179
Verification Accuracy 179
AHB Arbitration and Cycle Accuracy Issues 182
Modeling Summary 184
Synchronization 185
Types of Software 186
Other Metrics 186
Chapter 5: Advanced Hardware/Software Co-Verification 189
Direct Access to Simulation Memories 189
Memory Optimizations and Performance 195
Modes of Synchronization 199
Interprocess Communication 201
Mixing HDL and C Models 204
Implicit Access 207
Save and Restart 210
Post-Processing Software Debugging Techniques 212
Embedded Software Tool Issues 217
Debugging Co-Verification Issues 218
Chapter 6: Hardware Verification Environment and Co-Verification 221
Bus Monitor 221
Protocol Checking 231
Aligned Addresses 231
Issuing Idle Transfers 231
Assertions 232
Assertion Definitions 232
Assertion Approaches 234
Declarative Assertions 234
Procedural Assertions 236
Formal Property Language 236
Pseudo-Comment Directives 237
Post-Processing Simulation History 237
Assertions for Simulation Acceleration and Emulation 238
Testbenches Using Bus Functional Models 239
Directed Tests 240
Constrained Random Tests 241
Testbench Architecture 242
Functional Coverage 244
Compliance Suite 245
Software Verification 245
Software Print Statements 246
Summary 251
Chapter 7: Methodology for an Example ARM SoC 253
SoC Methodology Difficulty 254
Verification Efficiency 255
The Debugging Loop 256
Co-Verification Methodology 258
System Initialization and HAL Development 259
Diagnostics 259
RTOS and Device Drivers 260
Application Software 260
Testbench Development 260
Three Verification Phases 261
Example of ARM Verification Flow 263
Block and Subsystem Verification 263
Initial System Integration 264
Focused Hardware Verification 266
Hardware/Software Co-Verification 267
System Software Testing 268
The Co-Verification Engineer 270
Conclusion 272
Methodology Gridlock 273
Afterward 277
Index 279
| Erscheint lt. Verlag | 4.9.2004 |
|---|---|
| Sprache | englisch |
| Themenwelt | Kunst / Musik / Theater ► Design / Innenarchitektur / Mode |
| Sachbuch/Ratgeber | |
| Mathematik / Informatik ► Informatik ► Theorie / Studium | |
| Technik ► Elektrotechnik / Energietechnik | |
| Technik ► Maschinenbau | |
| ISBN-10 | 0-08-047690-2 / 0080476902 |
| ISBN-13 | 978-0-08-047690-2 / 9780080476902 |
| Informationen gemäß Produktsicherheitsverordnung (GPSR) | |
| Haben Sie eine Frage zum Produkt? |
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