3D IC Devices, Technologies, and Manufacturing
Seiten
2016
SPIE Press (Verlag)
978-1-5106-0146-8 (ISBN)
SPIE Press (Verlag)
978-1-5106-0146-8 (ISBN)
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Discusses the advantages of 3D devices and their applications in dynamic random access memory (DRAM), 3D-NAND flash, and advanced-technology-node CMOS ICs. Topics include the development of DRAM cell transistors and storage node capacitors; the manufacturing process of advanced buried-word-line DRAM; scaling trends of CMOS logic; and devices that may be used in the “post-CMOS” era.
The process of scaling integrated circuit (IC) chips has become more challenging as the feature size has been pushed into nanometer-technology nodes. In order to extend the scaling, engineers and scientists have attempted to not only shrink the feature size in x and y directions but also push IC devices into the third dimension.
This book discusses the advantages of 3D devices and their applications in dynamic random access memory (DRAM), 3D-NAND flash, and advanced-technology-node CMOS ICs. Topics include the development of DRAM cell transistors and storage node capacitors; the manufacturing process of advanced buried-word-line DRAM; 3D FinFET CMOS IC devices; scaling trends of CMOS logic; devices that may be used in the ""post-CMOS"" era; and 3D technologies, such as the 3D-wafer process integration of silicon-on-ILD and TSV-based 3D packaging.
The process of scaling integrated circuit (IC) chips has become more challenging as the feature size has been pushed into nanometer-technology nodes. In order to extend the scaling, engineers and scientists have attempted to not only shrink the feature size in x and y directions but also push IC devices into the third dimension.
This book discusses the advantages of 3D devices and their applications in dynamic random access memory (DRAM), 3D-NAND flash, and advanced-technology-node CMOS ICs. Topics include the development of DRAM cell transistors and storage node capacitors; the manufacturing process of advanced buried-word-line DRAM; 3D FinFET CMOS IC devices; scaling trends of CMOS logic; devices that may be used in the ""post-CMOS"" era; and 3D technologies, such as the 3D-wafer process integration of silicon-on-ILD and TSV-based 3D packaging.
| Erscheinungsdatum | 06.05.2016 |
|---|---|
| Reihe/Serie | Press Monographs |
| Verlagsort | Bellingham |
| Sprache | englisch |
| Maße | 152 x 229 mm |
| Gewicht | 455 g |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 1-5106-0146-5 / 1510601465 |
| ISBN-13 | 978-1-5106-0146-8 / 9781510601468 |
| Zustand | Neuware |
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