gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits (eBook)

The semi-empirical and compact model approaches

Paul Jespers (Autor)

eBook Download: PDF

2009 | 1. Auflage
XVI, 171 Seiten
Springer US (Verlag)
978-0-387-47101-3 (ISBN)

Infos

IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that restrict bandwidth. Which methodology to use in order to come across the best compromise(s)? Is synthesis a mixture of design experience combined with cut and tries or is it a constrained multivariate optimization problem, or a mixture? Optimization algorithms are attractive from a system perspective of course, but what about low-voltage low-power circuits, requiring a more physical approach? The connections amid transistor physics and circuits are intricate and their interactions not always easy to describe in terms of existing software packages.

The gm/ID synthesis methodology is adapted to CMOS analog circuits for the transconductance over drain current ratio combines most of the ingredients needed in order to determine transistors sizes and DC currents.

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In "e;The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits"e;, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com  allow redoing the tests.

Inhalt

Foreword 7
Contents 10
Notations 14
Sizing the Intrinsic Gain Stage 16
1.1 The Intrinsic Gain Stage 16
1.2 The Intrinsic Gain Stage Frequency Response 16
1.3 Sizing the Intrinsic Gain Stage 18
1.4 The gm/ ID Sizing Methodology 22
1.5 Conclusions 23
The Charge Sheet Model Revisited 25
2.1 Why the Charge Sheet Model? 25
2.2 The Generic Drain Current Equation 25
2.3 The Charge Sheet Model Drain Current Equation 27
2.4 Common Source Characteristics 29
2.5 Weak Inversion Approximation of the Charge Sheet Model 32
2.6 The gm/ ID Ratio in the Common Source Configuration 34
2.7 Common Gate Characteristics of the Saturated Transistor 37
2.8 A Few Concluding Remarks Concerning the C.S.M. 38
Graphical Interpretation of the Charge Sheet Model 39
3.1 A Graphical Representation of ID 39
3.2 More on the VT Curve 42
3.3 Two Approximate Representations of VT 43
3.4 A Few Examples Illustrating the Use of the Graphical Construction 46
3.5 A Closer Look to the Pinch-Off Region 52
3.6 Conclusion 53
Compact Modeling 54
4.1 The Basic Compact Model 54
4.2 The E.K.V. Model 55
4.3 The Common Source Characteristics ID (VG) 61
4.4 Strong andWeak Inversion Asymptotic Approximations Derived from the Compact Model 63
4.5 Checking the Compact Model Against the C.S.M. 63
4.6 Evaluation of gm/ ID 67
4.7 Sizing the Intrinsic Gain Stage by Means of the E. K. V. Model 68
4.8 The Common-Gate gms/ ID Ratio 70
4.9 An Earlier Compact Model 71
4.10 Modeling Mobility Degradation 72
4.11 Conclusion 79
The Real Transistor 80
5.1 Short Channel Effects 80
5.2 Checking the Validity of the Compact Model when its Parameters vary with the Source and Drain Voltages 82
5.3 Compact Model Parameters Versus Bias and Gate Length 89
5.4 Reconstructing ID (VDS) Characteristic 95
5.5 Evaluation of gx/ ID Ratios 97
5.6 Conclusions 104
The Real Intrinsic Gain Stage 105
6.1 The Dependence on Bias Conditions of the gm/ ID and gd/ ID Ratios ( MATLAB fig061. m) 105
6.2 Sizing the I.G.S with "Semi-empirical" Data 106
6.3 Model Driven Sizing of the I.G.S. 116
6.4 Slew-Rate Considerations 123
6.5 Conclusions 124
The Common-Gate Configuration 125
7.1 Drain Current Versus Source-to-Substrate Voltage ( Matlab fig071. m) 125
7.2 The Cascoded Intrinsic Gain Stage 127
Sizing the Miller Op. Amp. 132
8.1 Introductory Considerations 132
8.2 The Miller Op. Amp. 132
8.3 Sizing the Miller Operational Amplifier (MATLAB OpAmp. m) 140
8.4 Conclusion 153
How to Utilize the Data available under "extras. springer. com" 154
A1.1 Global Variables 154
A1.2 An Example Making Use of the "Semi-empirical" Data: The Evaluation of Drain Currents and gm/ ID Ratio Matrices ( MATLAB A12. m) 155
A1.3 An Example Making Use of the E.K.V Global Variables: The Elaboration of an ID( VGS) Characteristic ( Matlab A13. m) 157
The "MATLAB" Toolbox 160
A2.1 Charge Sheet Model Files 160
A2.2 Compact Model Files 162
A2.3 Other Functions 163
Temperature and Mismatch, from C.S.M. to E. K. V. 165
A3.1 The Influence of the Temperature on the Drain Current ( MATLAB A31. m) 165
A3.2 The Influence of the Temperature on gm/ID ( Matlab A32. m) 166
A3.3 Temperature Dependence of E.K.V Parameters ( MATLAB A33. m) 168
A3.4 The Impact of Technological Mismatches on the Drain Current ( Matlab A34. m) 169
A3.5 Mismatch and E.K.V Parameters (MATLAB A35.m) 171
E.K.V. Intrinsic Capacitance Model 172
Bibliography 176
Index 178

Produkt-Details

• Erscheint lt. Verlag: 1.12.2009
• Reihe/Serie: Analog Circuits and Signal Processing
• Zusatzinfo: XVI, 171 p.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik
• Themenwelt: Naturwissenschaften ► Physik / Astronomie
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: CMOS • Integrated circuit • large signal compact models • low-voltage, low-power analog CMOS circuits • micro-alloy transistor • parameter acquisition • Rom • sizing methodology • static-induction transistor • Transistor
• ISBN-10: 0-387-47101-4 / 0387471014
• ISBN-13: 978-0-387-47101-3 / 9780387471013