Ultra-Low Voltage Nano-Scale Memories (eBook)

Masashi Horiguchi, Kiyoo Itoh, Hitoshi Tanaka (Herausgeber)

eBook Download: PDF

2007 | 2007
XI, 346 Seiten
Springer US (Verlag)
978-0-387-68853-4 (ISBN)

Infos

Ultra-low voltage large-scale integrated circuits (LSIs) in nano-scale technologies are needed both to meet the needs of a rapidly growing mobile cell phone market and to offset a significant increase in the power dissipation of high-end microprocessor units. The goal of this book is to provide a detailed explanation of the state-of-the-art nanometer and sub-1-V memory LSIs that are playing decisive roles in power conscious systems. Emerging problems between the device, circuit, and system levels are systematically discussed in terms of reliable high-speed operations of memory cells and peripheral logic circuits. The effectiveness of solutions at device and circuit levels is also described at length through clarifying noise components in an array, and even essential differences in ultra-low voltage operations between DRAMs and SRAMs.

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Ultra-Low Voltage Nano-Scale Memories provides an in-depth discussion of the state-of-the-art nanometer and sub-1-V memory LSIs that are playing decisive roles in power conscious systems. Emerging problems between the device, circuit, and system levels are systematically covered in terms of reliable high-speed operations of memory cells and peripheral logic circuits. The effectiveness of solutions at device and circuit levels is also described at length through clarifying noise components in an array, and even essential differences in ultra-low voltage operations between DRAMs and SRAMs. Moreover, various kinds of on-chip voltage converters necessary to solve problems with internal power-supply managements are extensively discussed. This authoritative monograph addresses these design challenges for memory and circuit engineers as well as for researchers and students who are interested in ultra-low voltage nano-scale memory LSIs.

Inhalt

Preface 6
Table of Contents 8
An Introduction to LSI Design 13
1.1. Introduction 13
1.2. Basics of LSI Devices 13
1.3. Leakage Currents 26
1.3.1. Subthreshold Current 26
1.3.2. Gate-Tunneling Current 28
1.3.3. Substrate Current 29
1.3.4. pn-Junction Current 30
1.4. Basics of CMOS Digital Circuits 31
1.4.1. CMOS Inverter 32
1.4.2. NOR and NAND Gates 33
1.4.3. Cross-Coupled CMOS Sense Amplifier 33
1.4.4. Level Shifter 35
1.4.5. Charge Pump 35
1.4.6. Ring Oscillator 36
1.5. Basics of CMOS Analog Circuit 36
1.6. Basics of Memory LSIs 44
1.6.1. Memory Chip Architectures 46
1.6.2. Memory Cells 47
1.7. Basics of DRAMs 49
1.7.1. Read Operation 50
1.7.2. Write Operation 52
1.7.3. Refresh Operation 53
1.8. Basics of SRAMs 54
1.8.1. Read Operation 54
1.8.2. Write Operation 56
1.9. Basics of Flash Memories 57
1.10. Soft Errors 68
1.11. Redundancy Techniques 69
1.12. Error Checking and Correcting (ECC) Circuit 71
1.13. Scaling Laws 72
1.13.1. Constant Electric-Field Scaling 72
1.13.2. Constant Operation-Voltage Scaling 74
1.13.3. Combined Scaling 75
1.14. Power Supply Schemes 75
1.15. Trends in Power Supply Voltages 78
1.16. Power Management for Future Memories 80
1.16.1. Static Control of Internal Supply Voltages 82
1.16.2. Dynamic Control of Internal Supply Voltages 84
1.17. Roles of On-Chip Voltage Converters 85
References 86
Ultra-Low Voltage Nano-Scale DRAM Cells 90
2.1. Introduction 90
2.2. Trends in DRAM-Cell Developments 91
2.2.1. The 1-T Cell and Related Cells 91
2.2.2. Gain Cells 93
2.3. 1-T-Based Cells 96
2.3.1. The Data-Line Arrangement 96
2.3.2. The Data-Line Precharging Scheme 98
2.4. Design of the Folded-Data-Line 1-T Cell 98
2.5. Design of the Open-Data-Line 1-T Cell 115
2.5.1. Noise-Generation Mechanism 116
2.5.2. Concepts for Noise Reduction 118
2.5.3. Data-Line Shielding Circuits 121
2.6. Design of the 2-T Cell 121
2.7. Design of Double-Gate Fully-Depleted SOI Cells 123
References 126
Ultra-Low Voltage Nano-Scale SRAM Cells 129
3.1. Introduction 129
3.2. Trends in SRAM-Cell Developments 130
3.3. Leakage Currents in the 6-T SRAM Cell 132
3.4. The Voltage Margin of the 6-T SRAM Cell 134
3.4.1. Read and Write Voltage Margin 135
3.4.2. Signal Charge 136
3.5. Improvements of the Voltage Margin of the 6-T SRAM Cell 140
3.5.1. Lithographically Symmetric Cell Layout 140
3.5.2. Power-Supply Controlled Cells 141
3.5.3. Fully-Depleted SOI Cells 145
3.6. The 6-T SRAM Cell Compared with the 1-T DRAM Cell 149
Leakage Reduction for Logic Circuits in RAMs 161
4.1. Introduction 161
4.2. Basic Concepts for Leakage Reduction of MOSTs 162
4.3. Basics of Leakage Reduction Circuits 164
4.4. Gate-Source Reverse Biasing Schemes 168
4.4.1. Gate-Source Self-Reverse Biasing 169
4.4.2. Gate-Source Offset Driving 173
4.5. Applications to RAMs 176
4.5.1. Leakage Sources in RAMs 177
4.5.2. Features of Peripheral Circuits of RAMs 179
4.5.3. Applications to DRAM Peripheral Circuits 180
4.5.4. Applications to SRAM Peripheral Circuits 186
References 189
Variability Issue in the Nanometer Era 192
5.1. Introduction 192
5.2. Vt Variation in the Nanometer Era 192
5.3. Leakage Variations 193
5.4. Speed Variations of Logic Circuits 194
5.5. Variations in Vt Mismatch of Flip-Flop Circuits 195
5.6. Solutions for the Reductions 198
References 204
Reference Voltage Generators 207
6.1. Introduction 207
6.2. The Vt-Referenced VREF Generator 208
6.3. The Vt-Difference Vt VREF Generator 211
6.4. The Bandgap V 217
6.4. The Bandgap VREF Generator 217
6.5. The Reference Voltage Converter/Trimming Circuit 226
6.6. Layout Design of V ref Generator 232
References 235
Voltage Down-Converters 238
7.1. Introduction 238
7.2. The Series Regulator 240
7.2.1. DC Characteristics 241
7.2.2. Transient Characteristics 246
7.2.3. AC Characteristics and Phase Compensation 250
7.2.4. PSRR 269
7.2.5. Low-Power Design 272
7.2.6. Applications 274
7.3. The Switching Regulator 276
7.4. The Switched-Capacitor Regulator 279
7.5. The Half -VDD Generator 284
References 288
Voltage Up-Converters and Negative Voltage Generators 291
8.1. Introduction 291
8.2. Basic Voltage Converters with Capacitor 293
8.3. Dickson-Type Voltage Multiplier 306
8.4. Switched-Capacitor (SC)-Type Voltage Multipliers 313
8.5. Comparisons between Dickson-Type and SC- Type Multipliers 315
8.6. Voltage Converters with an Inductor 319
8.7. Level Monitor 323
A8.1. Efficiency Analysis of Voltage Up-Converters A8.1.1. Dickson- Type Charge Pump Circuit 325
A8.1.2. Switched-Capacitor-Type Charge Pump Circuit 328
References 331
High-Voltage Tolerant Circuits 333
9.1. Introduction 333
9.2. Needs for High-Voltage Tolerant Circuits 333
9.3. Concepts of High-Voltage Tolerant Circuits 334
9.4. Applications to Internal Circuits 336
9.5. Applications to I/O Circuits 339
9.5.1. Output Buffers 339
9.5.2. Input Buffers 342
References 343
Index 344

Produkt-Details

• Erscheint lt. Verlag: 4.9.2007
• Reihe/Serie: Integrated Circuits and Systems
• Zusatzinfo: XI, 346 p. 290 illus.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Mathematik / Informatik ► Informatik
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: Analog • Circuit • Circuit Design • DRAM • Generator • High voltage • Integrated circuit • Logic • LSI • microprocessor • nano-scale • Processor • Signal • SRAM
• ISBN-10: 0-387-68853-6 / 0387688536
• ISBN-13: 978-0-387-68853-4 / 9780387688534