Interconnect Noise Optimization in Nanometer Technologies (eBook)

Magdy A. Bayoumi, Mohamed Elgamel (Autoren)

eBook Download: PDF

2006 | 2006
XIX, 137 Seiten
Springer US (Verlag)
978-0-387-29366-0 (ISBN)

Infos

Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect

Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits

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Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.

Inhalt

Contents 6
LIST OF FIGURES 10
LIST OF TABLES 13
Preface 14
Acknowledgments 16
Chapter 1 INTRODUCTION 17
1.1 TECHNOLOGY TRENDS 17
1.2 MOTIVATION 18
1.3 BOOK OUTLINE 18
Chapter 2 NOISE ANALYSIS AND DESIGN IN DEEP SUBMICRON 20
2.1 NOISE 21
2.2 RELIABILITY 23
2.3 NOISE SOURCES 24
2.4 NOISE REDUCTION TECHNIQUES 28
2.5 NOISE ANALYSIS ALGORITHMS 40
Chapter 3 INTERCONNECT NOISE ANALYSIS AND OPTIMIZATION TECHNIQUES 44
3.1. SILICON TECHNOLOGY 44
3.2. INTERCONNECT NOISE MODELS 47
3.3. INTERCONNECT NOISE MINIMIZATION TECHNIQUES 50
3.4. INTERCONNECT NOISE IN EARLY DESIGN STAGES 53
3.5. CASE STUDY: PENTIUM® 4 57
Chapter 4 CROSSTALK NOISE ANALYSIS IN ULTRA DEEP SUBMICROMETER TECHNOLOGIES 59
4.1 ANALYTICAL EXPRESSIONS 60
4.2 TRANSMISSION LINE MODEL 60
4.3 SIMULATION RESULTS 64
4.4 DESIGN GUIDELINES 70
4.5 SUMMARY 71
Chapter 5 MINIMUM AREA SHIELD INSERTION FOR INDUCTIVE NOISE REDUCTION 72
5.1 INDUCTIVE COUPLING 72
5.2 PROBLEM FORMULATION 75
5.3 SHIELD INSERTION ALGORITHM 79
5.4 EXPERIMENTAL RESULTS 83
5.5 COMPLEXITY ANALYSIS 86
5.6 SUMMARY 86
Chapter 6 SPACING ALGORITHMS FOR CROSSTALK NOISE REDUCTION 87
6.1 SIMULTANEOUS WIRE SIZING AND WIRE SPACING IN POST- LAYOUT 87
6.2 POST GLOBAL ROUTING CROSSTALK SYNTHESIS 88
6.3 TIMING- AND CROSSTALK-DRIVEN AREA ROUTING 89
6.4 A SPACING ALGORITHM FOR PERFORMANCE ENHANCEMENT AND CROSSTALK REDUCTION 89
6.5 A POST PROCESSING ALGORITHM FOR CROSSTALK- DRIVEN WIRE PERTURBATION 90
Chapter 7 POST LAYOUT INTERCONNECT OPTIMIZATION FOR CROSSCOUPLING NOISE REDUCTION 91
7.1 MOTIVATIONS 92
7.2 PROBLEM FORMULATION 93
7.3 NOISE MODELING 94
7.4 MULTI SEGMENT NETS CROSSCOUPLING NOISE MODEL 98
7.5 MULTI CROSSCOUPLING NOISE MODEL 99
7.6 WIRE SPACING 100
7.7 POST LAYOUT RE-SPACING ALGORITHM 101
7.8 EXPERIMENTAL RESULTS 103
7.9 SUMMARY 105
Chapter 8 3D INTEGRATION 106
8.1 EXISTING 3D INTEGRATION TECHNOLOGIES 106
8.2 COMMERCIAL 3D DEVICES 108
8.3 3D IC DESIGN TOOLS 109
Chapter 9 EDA INDUSTRY TOOLS: STATE OF THE ART 117
9.1 MENTOR GRAPHICS 117
9.2 CADENCE 120
9.3 SYNOPSYS 129
9.4 ACCELERANT NETWORKS INC. 131
9.5 SILICON METRICS 132
9.6 MAGMA 132
Index 141
About the Authors 143

Produkt-Details

• Erscheint lt. Verlag: 20.3.2006
• Zusatzinfo: XIX, 137 p.
• Verlagsort: New York
• Sprache: englisch
• Themenwelt: Informatik ► Weitere Themen ► CAD-Programme
• Themenwelt: Informatik ► Weitere Themen ► Hardware
• Themenwelt: Technik ► Elektrotechnik / Energietechnik
• Schlagworte: 3D • algorithms • CAD • Complexity • Computer-Aided Design (CAD) • Integrated circuit • Interconnect • Layout • metal-oxide-semiconductor transistor • Optimization • Shield insertion • Simulation • Wire spacing
• ISBN-10: 0-387-29366-3 / 0387293663
• ISBN-13: 978-0-387-29366-0 / 9780387293660