Interconnect and Temperature Aware Unified Physical and High Level Synthesis
Seiten
2025
|
1st ed. 2026
Springer (Verlag)
978-94-007-1892-0 (ISBN)
Springer (Verlag)
978-94-007-1892-0 (ISBN)
- Noch nicht erschienen (ca. November 2025)
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This book addresses several fundamental design challenges in high-level synthesis of high-performance VLSI System-on-Chip circuits in advanced CMOS technologies. It proposes an integrated approach to power and thermal management during high-level synthesis.
The exponential scaling in CMOS transistor sizes over the past three decades have enabled spectacular advances in integrated circuit technology, allowing the integration of more than a billion transistors in modern very large-scale integrated (VLSI) circuits. Over the last four decades, transistor scaling has followed Moore's law, and according to projections made by the International Technology Roadmap for Semiconductors (ITRS), minimum feature sizes are expected to reach 22nm by 2012. The primary drivers for transistor scaling are the associated benefits of lower system costs, improved performance, and system reliability.
However, continuous device and interconnect scaling trends in deep submicron designs have created new challenges for integrated circuit designers such as increased interconnect delays due to rising parasitic resistance and capacitance of on-chip wiring, increased on-chip power densities, and performance and reliability problems posed by on-chip thermal gradients and thermal-hotspots. Thus, the major challenge is in achieving reliable, high-performance system implementations, all the way from the micro-architecture level down to the layout level. In order to realize such an implementation, a unified physical-level and high-level synthesis method becomes paramount, to ensure predictability of HLS design flows and minimize design iterations.
The exponential scaling in CMOS transistor sizes over the past three decades have enabled spectacular advances in integrated circuit technology, allowing the integration of more than a billion transistors in modern very large-scale integrated (VLSI) circuits. Over the last four decades, transistor scaling has followed Moore's law, and according to projections made by the International Technology Roadmap for Semiconductors (ITRS), minimum feature sizes are expected to reach 22nm by 2012. The primary drivers for transistor scaling are the associated benefits of lower system costs, improved performance, and system reliability.
However, continuous device and interconnect scaling trends in deep submicron designs have created new challenges for integrated circuit designers such as increased interconnect delays due to rising parasitic resistance and capacitance of on-chip wiring, increased on-chip power densities, and performance and reliability problems posed by on-chip thermal gradients and thermal-hotspots. Thus, the major challenge is in achieving reliable, high-performance system implementations, all the way from the micro-architecture level down to the layout level. In order to realize such an implementation, a unified physical-level and high-level synthesis method becomes paramount, to ensure predictability of HLS design flows and minimize design iterations.
Minimizing interconnect delays through net-topology aware high-level synthesis.- Layout-aware high-level synthesis for three-dimensional integrated circuits.- Crosstalk- aware high-level synthesis for macrocell based designs.- Temperature-aware unified physical-level and high-level synthesis.
| Erscheint lt. Verlag | 12.11.2025 |
|---|---|
| Zusatzinfo | Approx. 250 p. |
| Verlagsort | Dordrecht |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | algorithms • CAD • High-level synthesis • Nanometer CMOS Technologies • System-on-Chip • VLSI |
| ISBN-10 | 94-007-1892-6 / 9400718926 |
| ISBN-13 | 978-94-007-1892-0 / 9789400718920 |
| Zustand | Neuware |
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